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ADS1294: Timing after TI_STOP and TI_START commands

Krenar Tasimi
Prodigy 40 points
Part Number: ADS1294

I'm noticing an issue with the resynchronization of the clock after stopping and then starting the TI chip.  I assume the time base (I'm using 16kHz) will start once the start command is sent.  What I'm seeing is a discrepency of exactly 1 16kHz cycle, or 62.5us.  After sending the STOP command, waiting for 18 tclck cycles, then sending a START command, I observe a 62.5us difference in start times each time i stop and then start again.  It is seemingly random.  My application is time sensitive and therefore, I need to eliminate this variability.  Has anyone come across this, or know what might cause it?

  • 0
    TI__Guru 66386 points
    Hello Krenar,

    Thank you for your post.

    Have you read through the Settling Time section on page 51? After you send the START command, there will be a delay before the /DRDY signal transitions from high to low. Use Table 12 to calculate the settling time based on the DR[2:0] setting, Mode setting, and CLK period.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 40 points

    Hi Ryan,

    Thanks for your response.  I did consider the settling time needed before conversions start by adding a brief delay after issuing the start command. 

    I have a GPIO line on my processor configured for rising edge interrupt.  This interrupt starts the TI chip by sending the START command.  After sending data for 1s, the TI chip is then stopped, and waits for another rising edge to trigger an interrupt and start the chip back up.  If I measure the time from the rising edge (external signal) to the first data sample from the TI chip, it is either a constant value, call it X, or X+62.5us.  This is one clock cycle since I'm running at 16kHz.  It is never in between these values.  It has no fixed pattern whether the delay is X, or X+62.5us, it is seemingly random.  

  • 0 in reply to Krenar Tasimi
    TI__Guru 66386 points

    Hi Krenar,

    My guess is that the discrepancy between a delay of X and a delay of X + 1 tCLK is caused by when exactly the START command is recognized and latched by the ADS1294. The START command will be latched on the 7th SCLK falling edge. Depending on which master CLK edge this aligns with, the command may actually take effect one CLK period later.

    If you need this delay to be deterministic and constant while using the START SPI command, you will need to find a way to synchronize SCLK and CLK together.

    Another alternative might be to use a D-type flip-flop in a circuit like the one below. You can also toggle the START pin of the ADS1294 to begin conversions. Instead of controlling the START pin directly with a GPIO on your microcontroller, you would tie START to the output of the flip-flop and connect the GPIO to the /CLR pin. While /CLR is low, the output is also held low. Once /CLR is taken high by your MCU, the voltage on D (tied to DVDD) will appear on the output as soon as the next CLK rising edge is received. You could configure the ADS129x to output the internal clock onto the CLK pin with a simple register setting.

    Let me know what you think of this approach!

    Best Regards,