ADS1232: I have some basic questions about the specifications.

Hi Suzuki-san,

You asked the following questions:

1) Full-Scale Input Voltage

  -The specification is +/-0.5Vref/Gain. If the input is over the range, what is happened? [Bob] If you exceed the FSR, but the input is still within the absolute input range of the ADS1232, then you will see a full-scale output.  If the input exceeds +FS you will get a code of 0x7FFFFF, and if you exceed -FS you will get a code of 0x800000.

   -This specification is the range to ensure for PGA keeps to work linearly, correct? [Bob] Absolute input voltage range does not necessarily mean measurable input range.  The measurement range is determined by GAIN selection and reference voltage.  At a gain of 1, the measurement range is +/-2.5V for a 5V reference input (which also assumes AVDD is also 5V).  This allows for a full-scale range of 5V (+/-2.5V).  If you fix the input with AINN at GND, then the total measurement range is up to +FS, and you cannot measure negative values.  If you fix the AINN input to 2.5V, then if AINP can traverse from GND to AVDD and you can measure all voltages between -FS and +FS.

Using a gain greater than 2 (such as 64 or 128) the input range changes.  At gains of 1 or 2 the PGA is bypassed.  At gains of 64 and 128 the input range changes due to common-mode input range restrictions of the amplifier.  Input common-mode must be between GND+1.5V and AVDD-1.5V.  If the input is outside of this range then the input is outside the linear region of the amplifier.  The output of the amplifier is not rail-to-rail.

2) Normal mode rejection

   To secure this specification, we should input the signal within "Full-scale input voltage"(+/-0.5Vref/Gain), correct? [Bob] The normal input voltage must be within the measurement range of the ADC.  If the reference voltage input is 5V, as above, then you cannot apply a meaningful signal at AVDD and AGND.  The input voltage must be within the measurement range and not the absolute input range.

3) Relation between INL and ENOB, NFB [Bob] The INL is best described by looking at Figures 21 (Gain of 1) and 22 (Gain of 128).  The INL spec is endpoint fit throughout the entire measurement range of the ADC.  As it is not a fixed value throughout the input range, then it is difficult to compare to noise of the converter which is measured at a single point where the inputs are shorted.  The INL is worst case INL and the noise is best case.  Total error is a RSS of all error sources (which must be calculated to the same units before applying the RSS). 

ENOB is effective resolution taking into effect the noise distribution for 1 sigma of a Gaussian distribution.  Noise-free resolution is the resolution less any peak-to-peak noise (or the total distribution of noise).  Noise-free values are determined by direct measurement and the calculations for both ENOB and noise-free are shown in the ADS1232 datasheet above the noise tables on page 5.

4) External clock specification [Bob] In many cases the internal oscillator is good enough, but the accuracy and drift of the oscillator may cause issues when using 10 sps data rate to notch 50/60 Hz.  In this case an external oscillator can be used that is more precise and stable.  An external crystal can be used or an external crystal oscillator.  The range of clock options that can be applied ranges from as low as 200kHz up to a maximum of 8MHz.  An external clock frequency of 4.9152MHz will give the same output data rate and digital filter characteristics as the internal oscillator.

The data rate and digital filter characteristics will scale in proportion to an externally provided clock source.  4.9152MHz clock is one to one with the internal clock characteristics.  An external clock can be used to alter the notches in the digital filter or can speed up the output data rate.

The external clock is divided down before it is applied to the ADS1232 internal clock source tree.  This greatly reduces any issues with phase noise, jitter, duty-cycle , etc.. In general a crystal characteristics are dependent on external R-L-C values.  As the crystal outputs a sine wave, there are no issues with jitter, duty-cycle, etc.  An external oscillator could have some issues, but as mentioned, most of these are taken care of by the clock divider circuit.  The most common side effect of an external clock with high jitter is increased noise.  How much increase is difficult to say as just increasing the clock frequency will also increase the overall noise due to the faster clocks.  It is best when needing to use an external clock to use an accurate low jitter source.  When using a clock source such as a micro, the clock output from the micro will only be as good as the micro clock source.

5) Noise performance

 -The noise level is getting worse by Gain is bigger.

 -This is due to PGA's noise, correct? (the influence of PGA internal registance value??) [Bob] I believe you are confusing noise and resolution.  Input referred noise actually lowers with increases of gain.  This is shown by the RMS and Peak-to-Peak noise voltage values in the Noise Tables.  For example, let's look at gain of 1 and 2.  Note the RMS noise voltage at gain of 1 is 420nV, but at a gain of 2 is reduced to 270nV.

What is often confused is the resolution.  The value of a single bit changes with gain.  In the case of a gain of 1, the full-scale range may be 5V, but in the case of a gain of 2 it is 2.5V.  So the value of 1 bit of resolution changes with gain. At 5V FSR the resolution is 298nV, but the resolution at 2.5V FSR is 149nV.  As the FSR value reduces it takes 2 codes of 2.5V FSR to equal 1 code of 5V FSR.

The number of bits or the total resolution of the converter must take into account the sensor output range and gain to determine the sensor resolution.  If a load cell is used with a sensitivity of 2mV/V you will have much greater granularity of measurement at a gain of 128 then you will with a gain of 1 even though the resolution in the tables decreases.  The reduction in noise overcomes the reduction in number of bits.

6) Settling time

  -Though in case of single channel AD conversion, it maybe happen "abrupt changes".

  -Do you have something specification about "Abrupt" signal? [Bob]  The abrupt change is often consider to be a large step change in the input voltage.  This step is much like an end to end change such as going from near negative full-scale to near positive full-scale (or vice versa).  A more simple way to think about this is if you thing of averaging 4 or 5 samples together in a moving average.  If the input changes slowly with the mean, then you will not see much change from conversion to conversion.  If a new sample changes greatly from the mean, then you will see a significant change, but will take some number of samples to create a new mean (or settle) around that input voltage.

Best regards,

Bob B