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ADS7280 CMR

andrej.smit
Prodigy 10 points
Other Parts Discussed in Thread: ADS7280

 

Hi,

I have a problem with writing to ADS7280 CMR. No matter what I write to the A/D converter I recieve both channels and eaven when I don't send the command Read data (1101b). Is there some special set up that I don't know about it. It is always sending same information eaven tough I write different commands to CMR. The only logical explanation is that I don't write appropriate. 

This is the code:

 

unsigned int16 recieved=0;

output_low(sdo);

output_low(cs);

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(sdo);

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

//-------------send-0001b---------------------------------------//

output_low(sdo);

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

recieved=recieved<<1;

 

output_high(clk);

recieved=recieved|input(sdi);

output_low(clk);

//-------------recieved-A/D-conversion-result-----------------//

output_high(clk);

tag=tag|input(sdi);

output_low(clk);

tag=tag<<1;

 

output_high(clk);

tag=tag|input(sdi);

output_low(clk);

tag=tag<<1;

 

output_high(clk);

tag=tag|input(sdi);

output_low(clk);

// tag=tag<<1;

//-------------TAG-bit-recieved---------------------------------//

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

zero=zero<<1;

 

output_high(clk);

zero=zero|input(sdi);

output_low(clk);

//-------------Recieved-7-zeros-from-A/D-------------//

output_high(cs);

return recieved;

 

Andrej (Slovenia).

 

  • TI__Guru**** 180941 points

    Hi Andrej,

    When used with a normal SPI type peripheral, data into and out of the ADS7280 should be considered valid on the falling clock edge.  Since you appear to be bit-banging the device, you may not be setting it up correctly.  Could you possibly capture the SDI, SDO, SCLK and /CS lines on an oscilloscope for me while looping through a command byte of 0xExxx?  I'd like to see the phase relationship of the clock to input/output data.  You might also try writing various values to the configuration register and see what you get when you read that back.