• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 580 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS5295: ADS5295's ADCLKP/N outputs,two-wire is not 0.5x(sample rate in MSPS) MHz.

K.N
Expert 4445 points
Part Number: ADS5295
Other Parts Discussed in Thread: ADS5263

 Hello Team

 A question came from Customer.

 Of the following URL
www.tij.co.jp/.../ads5295.pdf

 It is a mention of DIGITAL OUTPUTS of DataSheet Page3.

ADCLKP and ADCLKN outputs (LVDS), two-wire     0.5x(sample rate in MSPS) MHz

　This is an error.

ADCLKP and ADCLKN outputs (LVDS), two-wire     1x(sample rate in MSPS) MHz

　I think that the above is correct.

　The reason is Figure 69 of DataSheet Page77.
　Figure 69. LVDS Output Interface Timing Diagram
　(Two-Wire, 12x Serialization, Byte-Wise and Bit-Wise Modes)

Input Clock, CLK Frequency = fS
Frame Clock, ADCLK　Frequency = 1x fS

 CLK and ADCLK are listed with the same frequency.

Best regards,
Keishi,Nishijima
Japan CSC

  • 0
    TI__Genius 12025 points
    Hi Nishijima-san,
    How are you?
    Thanks for helping the customer uses TI ADS5295 device.
    We will look into the customer's question on the Clock setting.

    Thank you very much!
    Best regards,
    Chen
  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi Keishi-san,

    How are you?

    Thanks for helping the customer use ADS5295 device.

    Very sorry for the confusion.

    Yes, The ADS5295 datasheet Page77 has some typos.

    The datasheet Page3 spec is correct.

    There is one similar with earlier revision device which is ADS5263 16-Bit device.

    ADS5263 device also has Two-Wire mode, CLK, Frame Clock,

    Byte-Wise mode and Bit-Wise Mode.

    (But ADS5295 has 12-Bit adc, v.s. ADS5263 has 16-Bit adc)

    Therefore, please take a look at the following ADS5263:

    datasheet's digital output plot (this plot is correct):

    (Hope you can understand why ADCLKP/M Freq is 0.5*Input CLK's Freq)

    Yes, I will discuss this customer's question in our group.

    Thank you very much for helping the customer.

    Have a very nice day!

    Best regards,

    Chen