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ADS1672: Are there special CLK supply pin's ?

Manfred Weise
Prodigy 20 points
Part Number: ADS1672

I am working on a PCB redesign which is using an ADS1672oPAG device. In the schematic they use separated power supply pins , for the CLK (pin 55 )  which are additional filtered.

Used Powersupply Pins are :  Pin53 = AVDD   and Pin 54 = AGND.

In your Datasheet and on the EVM Board I can't find any hint for this seperation .

Can you tell me if there is an internal separation  or if that was only a guess of the designer .

Best regards Manfred

  • 0
    TI__Guru 66256 points
    Hello Manfred,

    Thank you for your post and welcome to our forum!

    Can you please share the ADS1672 portion of the schematic? I'm not sure what you mean by "separated power supply pins."

    Most of the decoupling for the analog supply (AVDD) is needed near pins 11 and 12. Local 0.1 uF capacitors are recommended for pins 1, 7, 53, and 58. In the EVM layout, it appears that a separate connection is made from AVDD to each supply pin, with the exception of 11 and 12 being shorted together.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    Hello Ryan,

    thank for your really fast response. 

    Here the portion of the schematic .

    If the Supply AVDD / AGND  are not separated on the Die , this circuit  configuration on pin 53/54 makes no sense.  The signal clk+5V is used to

    supply the CLK driver IC too. We have got  lot of Noise in the measured results. 

     I shorted L51 and placed a 100R resistor in series of the CLK line. That step brought the noise significantly down.

    If I understand you right , we have no seperate "Analog Supply" for the CLK Input Buffer of the ADS1672 , so this filtering

    make no sense .  The filtered "clk+5V" could be used to supply the CLK buffer , so the "A+5V" might be not influenced by the fast clock edges.

    Best Regards and  hopefully the bits and bytes are with us  ;-)

    Manfred 

  • 0 in reply to Manfred Weise
    TI__Guru 66256 points
    Hi Manfred,

    To be honest, I'm not sure how the pins are connected to the die internally. That's something I'd have to ask a designer to look into, if you really want to know.

    I imagine that pins 53 and 58 are used for dedicated purposes inside the chip and that is why the EVM and datasheet show dedicated local decoupling capacitors. My recommendation would be to place at least a 0.1-uF cap next to each AVDD pin and at least 10 uF of bulk decoupling somewhere close to the ADS1672.

    Regarding the ferrite beads, I do not like placing them between the ADC supply pins and the supply source. This essentially chokes the chip when it demands an instantaneous increase in supply current. The 100 ohms in series with the CLK input probably helped because it helped to dampen reflections and slew the high-frequency edges. A 10-pF common-mode capacitor to ground near the CLK pin also helps to accomplish the same thing. This can help to reduce the noise that couples onto the ground plane.

    Best Regards,