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AFE5801 - Differential Analog input routing impedance

Nikhil Konaraddi59
Prodigy 150 points
Other Parts Discussed in Thread: AFE5801, CDCE62002, AFE5808A

Hello TI Team,

I am using AFE5801 for one of my project and I have following questions :

(1) I would like to know the differential impedance with which the input Analog signals (differential) be routed. Any recommendation on trace width and spacing that you advise?

(2) I am only using 6 channels at the moment. What do you recommend to do with the unused Analog inputs ? Similarly, what would you recommend to do with the unused LVDS outputs of corresponding unused analog channels

(3) To what supply are the signals PDN, RESET, SCLK, SDATA, SEN# referenced to ? In data sheet the maximum Input voltage on these pins is written as 3.6V and similarly for SDOUT it is mentioned as 1.8V? Can you please clarify this since I am driving these signals from an FPGA bank with 3.3V supply. 

(4) The signals PDN, RESET, SCLK, SDATA, SEN# need any external pull up/down resistors ? If so, to what supply should the pull up be referenced ?

Looking forward to your reply.

Thanks

Nikhil

  • 0
    TI__Genius 12025 points

    Hi Nikhil,

    How are you?

    Thank you for using TI AFE5801 device.

    We will look into your questions and reply to you very soon.

    Thank you again.

    Best regards,

    Chen

  • 0
    TI__Genius 12025 points

    Hi Nikhil,

    How are you?

    For your question #1:

    AFE5801 has high impedance differential inputs (INP, INM)

    (please take a look at the following plot from the datasheet.)

    So its input signal routing will be decided by your input signal structure:

    (for example, people usually are using 50 ohm impedance signal source,

    also our AFE5801 EVM is using 1:1 transformer and terminates with

    (25.5ohm+25.5ohm)//(5Kohm+5Kohm) equal to about 50ohm at the end of input signal.)

    Therefore, the trace width (can affecting impedance) is determined by what kind of signal source

    you are going to use.

    And also for the spacing between channel to channel,

    we suggest the spacing needed to be separated enough to avoid the signal crosstalk effect.

    For the question #2,

    For these two unused channels, we suggest please tie each input to GND

    (Note: the channel input pins must tie to series capacitors first and then tie them to GND after that.)

    For the unused LVDS output pins, although they are not used,

    please still terminate each unused differential pins with 100 ohm.

    Thank you!

    Have a nice day!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 150 points
    Hello Chen,

    Thanks for the reply. Can you also provide answers to my other questions 3 and 4 ?

    Nikhil
  • 0 in reply to Nikhil Konaraddi59
    TI__Genius 12025 points

    Hi Nikhil,

    How are you?

    For your question #3:

    Yes, the AFE5801 datasheet mentions

    when SDOUT output is set to high, its output voltage =1.6V ~1.8V (Not 3.3V).

    And we measured one AFE5801 EVM on the SDOUT pin.

    It showed its low level output voltage = 0V and its high level output voltage = 1.6V.

    So the datasheet is correct.

    For your question #4:

    Please take a look from the datasheet as below:

    All of the following pins (PDN, RESET, SCLK, SDATA)

    already have pull-down resistors inside the AFE5801 device.

    And the pin SEN# already has pull-up resistor inside the AFE5801 device.

    Thank you very much!

    Have a nice day!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 150 points
    Hello Chen,

    I have a question regarding the CLKINP and CLKINM pins in AFE5801 chip. I would like to use them as LVDS inputs. Is there a register that needs to be written to configure this as an LVDS input or is it automatically done. Additionally, will the LVDS receiver provide 100 Ohm impedance ? I am driving the clock here with CDCE62002 whose outputs are configured as LVDS. I wish to know if I need to terminate this with 100 Ohm or the LVDS receiver at the CLKINP and CLKINM pins already have the termination

    Looking forward to your reply

    Thanks
    Nikhil
  • 0 in reply to Nikhil Konaraddi59
    TI__Genius 12025 points

    Hi Nikhil,

    How are you?

    Thank you for using AFE5801 device and CDCE62002 device for your low jitter clock distributions.

    Yes, many of our AFE devices are using one clock source and connect to

    many AFE by using a clock distribution network circuit.

    For more information, please refer to: www.ti.com/lit/ds/symlink/afe5808a.pdf

    Here is one example:

    and for your clock input source,

    if your clock source is coming from LVDS configuration,

    here is the example showing how to connect from the clock source

    to AFE's clock input pins:

    For example, when the source clock comes from LVDS,

    then the 100ohm termination for AFE clock input pins

    is necessary.

    Please take a look.

    Thank you very much!

    Have a nice day!

    Best regards,

    Chen