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TLV5630: what is the usage of FS signal?

user5837914
Prodigy 20 points
Part Number: TLV5630

The datasheet said TLV5630 begin to read DIN with the falling edge of SCLK when FS is falling edge,

after the SPI read 16-bit data, the data will be loaded to the registers specified by the first 4-MSB of the data.

My question is:

1.Is FS mentioned in datasheet has to rise after the 16-bit data are read? what's the usage of FS in addition to activate the SPI?

2.The data sheet said TLV5630 can be set to CTRL0,CTRL1 and preset mode by specific 16-bit data,

but..when will the command  be effective after recieving it? When the FS becomes high?

3.If DIN possess 100-bit, how TLV5630 distinguishs each 16-bit packet? By the posedge of FS?

  

  • 0
    TI__Mastermind 46290 points
    Hello,

    The FS pin has two functions depending on which mode of operation the device interface is in, either microcontroller or DSP modes.

    In microcontroller mode the FS pin behaves as a chip select, when the pin goes low the SDI and SDO pins are enabled and data begins to be shifted in and out. A rising edge on FS triggers the latching mechanism of the input data.

    In DSP mode the FS pin is a frame sync pin, indicating when the inputs and outputs need to begin shifting data in. After 16 clocks, the data is latched in DSP mode regardless of the state of the FS pin.

    I hope this clarifies things.
  • 0 in reply to Kevin Duke
    Prodigy 20 points

    Kevin Duke said:
    , when the pin goes low the SDI and SDO pins are enabled and data begins to be shifted in and out.

    A rising edge on FS triggers the latching mechanism of the input data

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    1.Does it mean if I want to program TLV5630 in uC mode, then I just need to control the FS to be low, at this time,

    sending the SDI 16-bit data(packet) serially, and controlling the SCLK to be negedge to make SPI read it bit by bit,

    after 16-bit data is stored in SPI, I need to control the FS to be high to make SPI transfer the data

    before the next 16-bit packet comming, and the circuit in the TLV5630 will finish the task according to

    the transferred 16-bit data?   

    2.Does it means TLV5630 should distinguish the first bit of every 16-bit packet by the first negedge of FS and SCLK in every cycle,

    and use the posedge of FS to mark the ending of existing cycle?

  • 0 in reply to user5837914
    TI__Mastermind 46290 points
    Hello,

    Yes, I believe your understanding of the mechanics of the interface is correct.