Other Parts Discussed in Thread: LMK04828,
I'm using FMC144 mezzanine board from Abaco which has DAC38J84 IC on it. I'm also using Xilinx JESD204B core for setting up the interface. The clocks(Dclk and Sysref) are distributed over LMK04828 IC. The DACCLK is 1200MHz and SYSREF is 10MHz. The lane rate is 12Gbps and I'm using LMF:421.
Other settings are;
no interpolation, PA protect off, nco off, comlex multiplier off, qmc off, filters off, and using only 2 channels
On Xilinx JESD204 core side, it is the IP coreclk (1/40th of serial lane rate=300MHz by default) which samples the SYSREF. However, I don't know which clock samples the SYSREF on DAC38J84 side(no information in the datasheet). I assume it is DACCLK however there is also a divided jesd clock which is set by config37 register (@address 0x25). There is no information on jesd clock in the datasheet.
If it is the jesd clock which samples the SYSREF in DAC38J84, then I could divide 1200MHz DACCLK by 4 to get 300MHZ jesd clock that is equal to fpga JESD204 coreclk.(Thus LMFC alignment can occur properly)
If it is the DACCLK which samples the SYSREF in DAC38J84, then how could I align LMFCs on each side? There are 1200MHZ DACCLK and 300MHZ Xilinx JESD204 core clk which sample SYSREF on both sides. Shall I use different SYSREF values for each side in this case?
