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Use CDCE72010 to Provide CLK for ADS5560

TZ
Prodigy 110 points
Other Parts Discussed in Thread: CDCE72010, ADS5560

Dear community,

      I was planning to use CDCE72010 to provide CLK for ADS5560, but there are still some questions make me confused.

      e.g.1   ADS5560 is supposed to work at  the sampling rate of  40MSPS and the SNR is critical in my design, then how should I design the interface bewteen the CDCE72010 and ADS5560 ?

      e.g.2   For CDCE72010, the reference was constant at 10MHz, what should I note in choosing the VCXO ? How to design the freqency of the VCXO ?

      e.g.3   In the document SLWU061A "ADS61x9/55xxEVM User's Guide", I noticed that the following statement in 2.2.2.1

The clock input is converted to a differential signal by a Mini-Circuits™ ADT4-1WT, which has an impedance ratio of 4, implying that voltage applied on J19 is stepped up by a factor of 2.

      According to my understanding, if the impedance ratio of the transformer is 4:1, then the voltage ratio is 2:1 and the CLK signal will be degraded through the transformer. So what's the matter ?

     I'll very thankful for your help.

Regards,

TZ

  • 0
    Prodigy 110 points

    In addition, what kind of input type should I take for the reference CLK of CDCE72010, the single-ended or differential ? Does it significant in SNR critical application ?

  • 0
    TI__Guru* 78394 points

    Hi TZ,

    Could you share with us your input IF frequency and the expected SNR performance you are looking for? Depending on your application, you can either use LVPECL interface or LVCMOS interface with narrow band crystal bandpass filter. You can find out more from the following application note:

    http://focus.ti.com/lit/an/scaa092/scaa092.pdf

    The frequency of the VCXO should be chosen such that the output divider of the CDCE72010 can divide it down to the desired sampling frequency you are looking for. I have also asked the Clocks Group to comment on this forum post as well. They can offer more suggestions on the VCXO selection and reference clock selection you have asked in this forum. 

    Regarding your question on the impedance ratio of the transformer, the ADT4-1WT datasheet listed its impedance ratio in terms of secondary over primary (4:1). On the EVM, we placed the secondary side on the ADC clock receiver and primary side on the clock input. Therefore, the voltage ratio is 2:1 (secondary/primary), and the signal is stepped up 2:1. 

    Thanks,

    -KH

     

  • 0 in reply to Kang Hsia
    Prodigy 110 points

    Dear KH,

    The input IF frequency is 5MHz, and the expected SNR performance will be as nice as what expressed in the datasheet of ADS5560. That's to say, the additive clock jitter caused by the PLL is expected to be as low as possible.

    After reading the application note recommended by you, I think the LVPECL interface will be the better choice, because it have an advantage in SFDR for the ADC(according to Figure 8&9 in SLWU061A) and will make the circuit simpler. Would you agree with me ?

    Regards,

    -TZ

  • 0 in reply to TZ
    TI__Guru* 78394 points

    Hi TZ,

    For best SNR performance, I would recommend the LVCMOS output with narrow band crystal filter option. We have seen in the lab that this option has similar performance as our in-lab signal generator for clock source. However, since the IF of interest is fairly low, the SNR performance between LVPECL and LVCMOS should be fairly similar as long as the clock source is very clean. You can see this on Figure 8/9 in SLWU061A that you mentioned earlier.

    Regarding the SFDR, the clocking may not affect SFDR performance as much as SNR (unless there are spurs that caused by coupling). The SFDR between the two figures has only 1dB of difference (89dB vs 90dB). I would say this is a typical measurement variation. 

    -KH. 

     

  • 0 in reply to Kang Hsia
    Prodigy 110 points

    Dear KH,

    I have another question about the frequency of the VCXO. In my design, the reference frequency is 10MHz, and the output frequency of 40MHz is desired by using CDCE72010. But now I am not sure of the frequency of the VCXO. Generally speaking, the VCXO with higher frequency acts in worse phase noise, which can be compensated in a way by division with higher division factor before the output.          So what's the compromise way ? 

    -TZ

  • 0 in reply to TZ
    TI__Guru* 78394 points

    Hi TZ,

    please see below response from the clock's group:

    The customer can use 40 MHz VCXO. Typically VCXO frequency is chosen based on highest application frequency. Higher frequency VCXO is expensive. As long as phase noise performance is met for the applications, he should be fine.

    Depending on VCXO performance sometimes divided output from VCXO shows better phase noise – but this is not true for all cases.

    -KH

  • 0 in reply to Kang Hsia
    Prodigy 110 points

    Hi KH,

    Thank you very much !

    -TZ