DAC37J84: Power Supply Noise Level Requirement

Kiran,

We do not have specific requirements for these rails. We can only provide general guidelines at this point.

The sensitivity of the power supplies with respect to ripple is similar to the ground plane and power plane layout that we have discussed before:
e2e.ti.com/.../718266

The most critical power supplies are the PLL/VCO (if you are using on-chip PLL) and also the VDDCLK (the DAC sampling clock buffer). Any noise coupled onto these rail will modulate the noise onto the sampling clock, and cause the output phase noise to increase proportionally. We highly recommend the use of LDO on these rails. TI has some nice low noise RF LDOs for this application. Be careful of using LDOs with internal charge pump to bias the LDO, we have seen cases where the charge pump noise gets coupled through to the output.

the least critical power supplies are the DVDD (all the digital power supplies for the FIR/NCO/and other mathematics). You may be able to supply it through DC/DC power supplies for efficiency, and be sure to add some ferrite bead near the switching frequency to avoid switching frequency couple onto the DAC itself.

If you are sharing power supplies, it is important to keep in mind that DVDD typically draw the most amount of current. The spreading of the power traces to various devices typically have PCB trace loss. Therefore, you may need to elevate your DVDD supply just slightly to compensate for the voltage drop.

-Kang