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DAC38J84EVM: SYNC not stable

Iranna Chougala
Prodigy 30 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: ADS42JB49EVM, , ADS42JB49, DAC38J84

Hi,

I have DAC38j84EVM and KC705 connected. DAC configuration is LMF_148, DAC input data rate 39.0625 MSPS, DAC output data rate 156.25 MSPS and line rate is 3.125 Gbps. External clock frequency is 312.5 MHz and it is generated from ADS42JB49EVM (SMA output clock port).

On FPGA, I see that SYNC is not stable and is toggling. DAC alarm shows Elastic Buffer Overflow set. If this error is disabled for SYNC request, the link is stable. What causes this error?

I have attached DAC config file GUI_DAC38j84_148_3p125GBPS.cfgAlso I need a clarification on DAC sampling rate. I have ADS42JB49 and DAC38j84 connected through 2 KC705 boards. My ADC sampling rate is 156.25 MSPS and line rate of 3.125G (LMF_221). For DAC (LMF_148) to have same sampling rate and line rate, what is the valid configurations on input data rate and output data rate.

ADC being 14 bit and DAC 16 bit, cause any issue? 

Any help will be greatly appreciated. 

Thanks,

Iranna

  • 0
    Prodigy 30 points
    I tried with changing K value from 5 to 14 and RBD value to K-1 for this setting I am seeing SYNC is stable. But when I tried for K as 15 and RBD as 14 SYNC toggling.
    I want to know is there any relation for setting K and RBD value.
  • 0
    TI__Guru* 78404 points
    Hello Irana,
    The following training material on JESD204B will help you understand the release buffer point and also the relationship to K value (i.e. number of frames per multi-frame or LMFC period).
    www.ti.com/.../slap159.pdf

    The JESD204B document (available on the JEDEC website, free to download as long as you register), also discusses the optimal RBD setting and have various illustrations on the JESD204B link.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 30 points
    Hi Kang,
    Thanks for your reply.
    I will go through the material and get back to you. Can you please give me clarification on below questions also

    I have attached DAC config file GUI_DAC38j84_148_3p125GBPS.cfgAlso I need a clarification on DAC sampling rate. I have ADS42JB49 and DAC38j84 connected through 2 KC705 boards. My ADC sampling rate is 156.25 MSPS and line rate of 3.125G (LMF_221). For DAC (LMF_148) to have same sampling rate and line rate, what is the valid configurations on input data rate and output data rate.

    ADC being 14 bit and DAC 16 bit, cause any issue?
  • 0 in reply to Iranna Chougala
    TI__Guru* 78404 points
    Iranna,

    You can read up on some training materials regarding the basics of ADC and DAC. The data rate I believe you are referring to are the data rate from base band before the ADC and DAC (also after decimation and before interpolation).

    If you are talking about such data rate, and in order for the line rate to match, most likely the LMFS of the JESD will also have to match as well. The reason that the DAC JESD rate matches ADC JESD rate in your case is because the DAC has 4 converters while the ADC has 2 converters, hence the rate matched even the LMFS did not match.

    I am not sure where you are coming from regarding the valid configuration on input data rate and output data rate. These rates are user selected and decided based on system requirement. Without system requirement, all modes are pretty much valid.

    some materials are:
    www.ti.com/.../slaa523a.pdf

    The ADC being 14bit while the DAC being 16 bit will be an signal to noise requirement (SNR) in your application. This again depends on your end application requirement. TI cannot decide for you. sorry.

    -Kang