In the reference schematics, we are seeing some intermediate voltage transitions to generate the needed voltage for the ADC. Any specific reason for this? Is it mandate to follow in our application circuitry? Please share your feedback. Your timely response is highly appreciable.
Following are the power tree:
5V---> 3.7V-->3.3V--->DAC
5V---> 3.7V---> 3.0V--->DAC
5V--> 2.3V-->1.9---> DAC
2.3V--->1.9V--> DAC
2.3V--->1.15V---> DAC
We have followed the below power sequence:
5V--> 3.3V---> DAC
5V--> 3V---> DAC
5V--> 1.9V---> DAC
5V--> 1.9V---> DAC
5V--> 1.15V---> DAC
Please suggest which is the right way to give power tree for ADC considering noise issues etc.
Thank you,
K.Harsha
