DAC FMC adaptor LPC or HPC?

HI,

I am trying to use the following hardware combination.

Can you please guide me whether they are compatible or not.

http://www.xilinx.com/products/devkits/EK-S6-SP601-G.htm   (FPGA board)

http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html  (adapter card)

ADC EVM cards which are listed in the above page.

NSS

Hi,

Yes,  All those ADC EVMs are intended to work with the FMC_ADC_Adpater into the FPGA development platform.  If you look at all those TI ADC EVMs, you would see that they all use the same Samtec connector for the digital connection, and all can connect to the TSW1200 Capture Card.  The FMC_ADC_Adapter makes sure to connect the DDR bit clock to a clock capable input on the FPGA, and all the rest of the LVDS pairs to pins on the FPGA that are LVDS capable with on-chip termination capability.

Keep in mind that the actual location of the LVDS signals in the connector will vary greatly from one EVM to the next, such as how many pair are used and which pair would be least-significant vs. most-significant.  So the FPGA code would have to be written to look for the data to come in on different locations depending on the family of EVM.  That is what the TSW1200 does - the ADC selection influences which inputs the data is expected to be found at.  Some EVMs may even have the polarity of the LVDS pairs swapped which requires an inversion in the FPGA, which is not a problem once you know about the detail. 

That is a long list of EVMs, and there may be details that are important for one or another EVM family.  For example, the ADS5400 EVM allows the option to use dual-busses out of the ADC, but there are not enough pins in the FMC connector to route two busses, so single bus option into the development platform is the only choice if the FPGA can handle the speed for that device.  Or the ADS55x7 family EVM can only be used if it is the *new* style EVM - our orignal EVM for the ADS55x7 did not use the Samtec connector and thus would not be suitable for this adapter card.  

But once you identify the EVM of interest, the User Guide for the EVM that is available on the web will list the schematics which include the pin assignment to the Samtec connector.  The schematics for the adapter card are also available on the web.  When you choose a development platform, you then can map out the conenctions from the data converter to your FPGA so that your constraint file can get the pin assignments correct.

Regards,

Richard P.

Thanks for your reply.

I have to work with ADS6445 EVM.

I have checked the manual and connector details. They appear to match.

please let me know if they are any electrical issues in interfacing.

http://focus.ti.com/docs/toolsw/folders/print/ads6445evm.html

http://www.xilinx.com/products/devkits/EK-S6-SP601-G.htm   (FPGA board)

http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html  (adapter card)

thanks

NSS

Hi,

The ADS6445 EVM will match up to the FPGA development platform by way of the adapter card, but this is one of the EVMs that has some details that you would wish to be aware of.

The way we deserialize the sample data in the TSW1200 is that we use the bit clock to clock the input DDR cell, and we treat the frame clock like just another data pair that happens to have a known pattern of 11110000 (in 2-wire mode 16bit mode with 2 zeros padded on the msb's of the sample). Then we look for the low to high position of the data on frame clock to know when to move the data being deserialized into a parallel register to hold the reconstructed sample data.   This way requires the frame clock to be treated like any other data pair.

The original (revision A) FMC_ADC_Adapter card routed the frame clock to a clock input because the FPGA vendor saw 'clock' in the name of the signal.  So we spun the adapter card to move frame clock to a data pair input.   If you choose to design the interface the way we did, then you would want to be sure you get the latest revision (revision C) of the adapter card, which is what we are building now.   If the old stock hasn't been flushed through the order process and you get the wrong one then we would swap it out for you to be sure you get the one you need.   Moving the frame clock to a data pair was one of the main reasons we revised the original adapter card.

If you prefer to bring frame clock into a clock input and then use a digital clock manager and try to use the Xilinx ISERDES element (as suggested in an app note from Xilinx), then you would want to order the adapter card and we could get the original revision card to you for that case also.  

There are no electrical issues that i know of to worry about for the LVDS signals from the ADC into the FPGA.

Regards,

RP