ADS5263: FPGA LVDS interface

Gauthier Auvray

Part Number: ADS5263

Hi,

I would like to interface a quad channels ADS5263 in LVDS/2wires/8xSerialization mode to a FPGA.

I was wondering if it would be possible to use the frame clock (ADCLK) to drive a PLL to generate the bit clock inside the FPGA (bit clock LCLK from ADC is therefore not used).

Timing closure at high speed (ADC at 80Msps) is tricky to achieve.

Since the frame clock seems to be generated the same way as data the idea is to save timing margin compared to the using of bit clock LCLK to latch data.

Unfortunatly there is no timing infomation in the datasheet concerning the data position relative to frame clock...

What is your opinion about this method?

Best regards,

Gauthier

over 7 years ago

0 Chen Kung over 7 years ago

TI__Genius 12025 points

Hi Gauthier,
How are you?
Thanks for using ADS5263 device.
We will look into your concern and will reply to you soon.

Thank you very much!

Best regards,
Chen

0 Chen Kung over 7 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi Gauthier,
Thank you for using ADS5263 device.
yes we also connect the ADS5263 output signal LVDS pins to FPGA (on our TSW1400 EVM).
We don't know what kind of FPGA you are going to use.
But before trying to using your method,
there are many things needed to be covered.
Please look at the following application note from TI:
Understanding Serial LVDS Capture in High-Speed ADCs
www.ti.com/.../sbaa205.pdf
And see if your FPGA can also follow the same method (please see the file from the TI website).

Thank you very much of using ADS5263.

Best regards,
Chen

0 Gauthier Auvray over 7 years ago in reply to Chen Kung

Prodigy 110 points

Hi Chen,

Thank you for this answer.

We use an Intel CycloneV GX (5CGXFC9E6F35C7) FPGA which doesn't seem to have DPA (Digitla Phase Alignment circuitry).

I have already implemented capture scheme using delays (Figure 4-2 in sbaa205.pdf) and timings are met with a sampling clock up to 40Mhz (data rate of 320Mbps).

At higher frequency timings are not met at all corner cases.

I wanted to try ALTLVDS_RX but with the frame clock as input clock. Since the frame clock is aligned with data, doing this way supress the need of frame alignment (bit slip).

Thanks,

Gauthier

0 Chen Kung over 7 years ago in reply to Gauthier Auvray

TI__Genius 12025 points

7360.TSW1400_D_SCH.pdf

Hi Gauthier,

Thank you for detail information.

The ADS5263 EVM is running with a data capture card TSW1400 EVM

(because LVDS signals' Timing is a big crucial.)

which is using Intel (used to be Altera) EP4SGX70 FPGA unit.

Please take a look at the attached schematics for TSW1400 EVM.

If you want to use the FPGA which is designed well used for capturing LVDS signals?

please contact with the FPGA company to verify and make sure

if that FPGA device can fit your LVDS signals' request.

Thank you for using ADS5263 device.

Best regards,

Chen

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ADS5263: FPGA LVDS interface