ADS8555: BUSY/INT structure

Hi, Cynthia san

ADS8555 data sheet (SBAS531D) page29 Please tell me the timing in Figure35.

Currently we are testing ADS8555, but BUSY does not become H-Level.
(We maintain L-Level)

Normally we will use the device in Haerware mode,
Immediately after turning on the power supply, set Auto-NAP in Software mode and then perform data conversion in Haerware mode.

I have a question,
BUSY changes from" L → H → L" immediately after resetting RESET from" H → L" at the timing of Figure 35.

1. After RESET is released, does BUSY go high?
2. Is BUSY being H in the middle of conversion operation?
3. Is this conversion data valid?
4. There is no SCLK at this timing. Does the operation immediately after RESET synchronize with SCLK?
   Or is it synchronized with built-in CLK?

I am designing software, but I have difficulty with less information.
Do you have any application notes that will help you?
Is it also available?

best regrads
cafain

Hello,

The BUSY signal indicates when the conversion phase of the conversion cycle is ongoing. It is triggered with any rising edge of CONVST signal and remains high until all channel data is latched in the output registers. If you are not seeing a BUSY signal, this is an indicator that you are in fact not completing any conversions. This most likely has to do with timing issue, timing is a common issue.

In the datasheet, Figure 35 is not trying to focus on timing; it is showing the sequence of events to program the control register based on the interface being used. The timing for these though are all based on the figures 1 thru 3, which break down and provide specific timing for reading and writing depending on the interface used.

I suggest writing to the registers, and then reading those registers back to confirm the registers were correctly programmed. Once this works correctly, you can focus on conversions using AutoNAP mode. Suggest using a known DC value, and comparing the expected output with the measured output. Using an oscilloscope with probes on the digital communications line will help further debug proving a visual representation of what is going on in addition to your software developed.

In auto_NAP mode, the time to complete a conversion is longer and thus reduces the maximum throughput of the device. A complete conversion in this mode takes 24.5 clock cycles. Are you taking this into account when creating the firmware to communicate to the device?

 The device can use an external conversion clock, or an internally generated clock, the default is the internally generated clock. When the device is reset, all modes are changed back to the default, meaning the internally generated clock.

Regards

Cynthia

Hi, Cynthia san

Serial data write/read operation

I confirmed the operation of BUSY and I was satisfied.
Please let me have another question.

When setting values are written to CR,
Enter the set value to be written to CR in DB13/SDI(2pin) and input the serial clock to DB6/SCLK(11pin).

To check whether the set value to CR is written correctly, read back.

Q1:When serial clock is input to DB6 / SCLK (11 pin), which terminal outputs serial data?
Q2:Is it output to DB8/SDO_A (7pin)?
Q3:Please tell me the operation method when reading CR serial data.

I understand that they all run in soft mode.

best regards
cafain