ADS1672: Minimum value of tDRPW

Hi Shinchi,

Welcome to our e2e forum! Can you please let us know a bit more about your setup? How fast is the SCLK? How are you comtrolling the START pin?

Hello Morita-san,

Thank you for your post.

We'll ask a designer to look into this one. Would it be possible to capture SCLK in the same image as CLK and /DRDY? Additional details about the device configuration will be necessary as well, please let us know as much as you can about the customer's setup.

Best Regards,

Hi Tom and Ryan,

Thank you very much for your reply.

The following is the customer's setup.

●Configuration

・SCLK_SEL=1　　　　 ：Pull-up to 3.3V

・DATA RATE[1：0]=11　 : Pull-up to 3.3V

・LL_CONFIG=1 　　　　：Pull-up to 3.3V

・FPATH=0 　　　　　　：Connected to GND

SCLK is about 240 ns with the same frequency as CLK.

The START pin is controlled from the FPGA,It is fixed from the low to High after turning on the power supply.

The Oscilloscope waveform is attached.

ADS1672_Waveform_GOOD_181031.pdf

ADS1672_START signal rising waveform_181029.pdf

I would like to isolate the cause of whether the short pulse width of DRDY is due to device failure or normal width.

Best regards,
Morita

Hi Morita,

Can you also clarify the meaning of 'Bad' from the original post as well as 'leads to error'? Is the conversion data erroneous or is it just the short DRDY signal?

Hi Tom,

Thank you very much for considering this question.
This issue is effecting our customer's production schedule, so we appreciate your quick response.

And I am sorry for the incomplete details.
The "Bad" in the original post is about DRDY pulse width.
"Leads to error" means the erroneous reading at FPGA. Because of the short DRDY pulse the
FPGA is not able to recognize the DRDY pulse and hence the error.

We would like to know if this kind of behavior is a possible scenario with ADS1672's use cases?
And what could be the possible reasons.

Best Regards
Morita

Hi Tom, Ryan

Any suggestion on this issue.
This issue needs to be closed immediately as the production line will be stopped until there is a conclusion.

Could you please let us know if you have any comments on the above question.

Best Regards
Morita

Hi Morita,

In the PDF plots you sent for 'ADS1672_Waveform_GOOD' and the 'ADS1672_Start' signal, I suspect that there was bandwidth limiting enabled on the scope (I don't understand why you are blanking out portions of the display).  In the original in-line plots, I suspect BW limiting was turned off.  Can you also provide us with a plot similar to the 'GOOD' but showing the 'BAD' behavior?  You seem to be running with a relatively slow tCLK, but that should not be causing this sort of problem.  There may be noise getting into the START signal or perhaps the SCLK/TCLK causing problems as well.  What is the status of /CS and the other control pins?

Hello Morita-san,

'ADS1672_Waveform_GOOD' clearly shows sufficient delay between /DRDY and the first SCLK rising edge, as well as sufficient delay between the last SCLK falling edge and the next /DRDY. Can you please share the same scope capture for the 'Bad' response with CLK, SCLK, /DRDY, and START? We need to see if the device is completing a conversion during an SPI read. 

Best Regards,

Hello Morita-san - do you have any updates?

Hello Ryan,

I have not got the same scope capture at 'Bad' response yet.

I will keep you updated.

What is the reason why the pulse width of DRDY changes under the same conditions?

Which signal or clock affects the pulse width of DRDY?

Best regards,
Morita

Hello Ryan,

I am sorry for the incomplete information.

Our customer has been continuously trying to re-produce this behavior but unfortunately
there are not able to re-produce the same issue.

But, the production line is stopped because of the uncertainty of this issue and its cause,
we need a conclusion to ask the customer to continue with the production.

If we can say that DRDY pulse width won't be such short duration in any possible scenario,
we can just ask them to replace the IC and continue with the production.

Just in case we would like to know which are the signals we should measure along with DRDY
to troubleshoot this issue? START/SCLK/CLK//CS/DOUT.

We would like to know if this kind of behavior is a possible scenario with ADS1672's use cases?
or else there is something wrong with that particular IC, so it should be replaced.

Best Regards
Morita