• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 524 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1282: Mux Channel Switching

santosh balakrishnan37
Intellectual 380 points
Part Number: ADS1282

Hello, 

I know this question has been asked and answered before. But i cannot find the the thread - so apologies in advance. 

My application requires both input channels on ADS1282 and our plan is/was to reprogram the mux so that we could sample the signal one after the other. 

General idea is :

Change Config 1 MUX , Issue Read Data wait for data ready, read data

Change Config 1 Mux to Channel 2, Issue Read Read Data Command, Wait for Data Ready, ready data

Changing config 1 mux from Channel 1 to Channel 2 is not working. I can switch channels as long as i do that as part of configuration. 

How fast can the channels be switched? All the data access is happening as part of interrupt service routines, and my plan was to issue commands back to back. Is this possible for on this chip?

On read registers i am putting in about 4 uS delay between bytes and that seems to be working fine. The ADC is clocked with a 4 MHz clock, and SPI is running at 2 MHz. Targeted data rate is 2KHz. 

Would appreciate any help/pointers.

Thanks

santosh

  • 0
    TI__Mastermind 44640 points
    Hi Santosh,

    Sorry for the delayed response.

    The settling time of the FIR filter is ~63 conversion periods, while the settling time of the SINC5 filter is ~5 conversion periods. Therefore when muxing between the two channels, the effective data rate while muxing needs to be divided by 5 or 63, depending on which filter mode you are in.

    The 4us dealy might be okay because of ther digital delays invoved in the SPI peripheral of your micron controller, but the ADS1282 datasheet recommends 24/fCLKs between consecutive command bytes, which works out to about 5.86 us, so I would recommend increasing your delay a bit just to be safe.

    The following E2E threads might have some relevant info for you:
    e2e.ti.com/.../1952215
    e2e.ti.com/.../2510610

    Best regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 380 points
    Chris,

    Thanks for the response. Thanks for the links, those were the ones i was looking for - i need to implement pretty much exactly the same scenario that Mahesh described for his user. I have few more questions -
    a) you mentioned with 16kSPS data will be ready in 408uS - can the device we configured for 16kSPS and assuming a 4.096MHz clock, shouldn't the data be ready in 63uS? What am i missing?
    b) When i attempted to do switch channels - Write Config 1 register, and then issue RDATA - the chip seems to be going dead - i.e no more DRDY going low. Not sure what i am doing wrong. However if i issue the config 1 register update when i boot up, the register update seems to hold.

    If i put the chip in RDATAC mode, can i switch channels between DRDY at all?
    That thread was great teaser, stops right where one thinks here is the anwser :).

    Additional question is - should i add another ADS1282 to handle the second channel instead of muxing.

    Thanks
    santosh
  • 0 in reply to santosh balakrishnan37
    TI__Mastermind 44640 points

    Hi Santosh,

    santosh balakrishnan37 said:
    a) you mentioned with 16kSPS data will be ready in 408uS - can the device we configured for 16kSPS and assuming a 4.096MHz clock, shouldn't the data be ready in 63uS? What am i missing?

    When continuously converting you will see the nominal data rate with new data every 63us; however, the first conversion result will be delayed by roughly five conversion periods because the SINC5 filter averaging the last five results, but when first starting a new conversion (and when switching channels) it has no history to go off of and so the ADC internally collects five conversions before /DRDY goes low to indicate that you have a "settled" conversion result. In the case of the FIR filter it is closer to 62 or 63 conversion periods for the first settled result due to the many filter taps of the FIR filter.

    santosh balakrishnan37 said:
    b) When i attempted to do switch channels - Write Config 1 register, and then issue RDATA - the chip seems to be going dead - i.e no more DRDY going low. Not sure what i am doing wrong. However if i issue the config 1 register update when i boot up, the register update seems to hold.

    Are you waiting for /DRDY to go low before reading the data? Also, are you putting hte device into SDATAC mode before trying to write to the device registers?

    Keep in mind that writing to the registers causes the current conversion to restart (i.e. the digital filter's conversion result history is reset) and so you will have to wait for the digital filter to settle again. Also, I believe register writes are ignored while you are in RDATAC mode, so try issuing the SDATAC command before trying to write to the registers.

    santosh balakrishnan37 said:
    Additional question is - should i add another ADS1282 to handle the second channel instead of muxing.

    If you need to measure two channels simultaneously, definitely. Otherwise if you can afford to MUX between the two channels, you'll have to decide if the digital filter setting time is too long to allow you to sample the two channels as quickly as you want.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Intellectual 380 points
    Chris,

    Really appreciate your detailed responses.
    >>Are you waiting for /DRDY to go low before reading the data? Also, are you putting hte device into SDATAC mode before trying to write >>to the device registers?
    I do a SDATAC on startup, and i trigger the read when DRDY goes low. The sequence i follow is issue RDATA, interrupt on DRDY high to low, read data on SPI. But if i update config 1, DRDY does not go low after that on an RDATA, and i don't read data. I have tried inserting delays between WREG and RDATA, but that does not seem to help.

    Thanks
    santosh
  • 0 in reply to santosh balakrishnan37
    TI__Mastermind 44640 points
    Hi Santosh,

    What is the command sequence you are using for the WREG command to the CONFIG1 register?

    Is it possible that in the WREG command you are setting the "nnnnn" bits to a non-zero value? In this case, the ADC will interpret your RDATA command as the next data byte to write into the HPF0 register. My guess is that the ADS1282 might be waiting for you to complete the WREG command (thinking you are writing to multiple rgisters) before it begins the next conversion.

    Best regards,
    Chris
  • 0 in reply to Christopher Hall
    Intellectual 380 points
    Chris,

    This is command sequence i was sending to switch channels
    0x42 - 0x40 | register 02
    0x00 - number of registers to write - 1
    0x18 - Select mux 01
    0x12 - RDATA command.

    I was expecting to see DRDY go low after conversion time once RDATA was issued. But ADS just went silent.

    Thanks
    santosh