Other Parts Discussed in Thread: ADC32RF80
Good day,
We are currenly designing a JESD204B receiver core on a Virtex-7 FPGA that recovers data from an ADC32RF45 clocked at 2.8 GHz.
The ADC is configured in DDC bypass mode and is set to produce a ramp pattern.
We are able to receive data of the CGS and ILA stages succesfully, but the data provided afterwards is not as expected.
Even though there is a consistent pattern in the data, it is not a ramp pattern.
This is the configuration information that we are writing to the JESD Digital Page.
0x4002, 0x00
0x4003, 0x00
0x4004, 0x69
0x7002, 0x0F
0x6002, 0x0F
0x7037, 0x01
0x6037, 0x01
0x7001, 0x80
0x6001, 0x80
0x7007, 0x0F
0x6007, 0x0F
0x7003, 0x01
0x6003, 0x01
0x7032, 0x3C
0x6032, 0x3C
0x7033, 0x3C
0x6033, 0x3C
0x7034, 0x3C
0x6034, 0x3C
0x7035, 0x3C
0x6035, 0x3C
0x7036, 0x40
0x703C, 0x01
As I understand this configuration info should allow us to configure the ADC to be in DDC bypass mode and to produce a ramp pattern. I assume the reason for our problem is that we are not configuring other registers correctly.
Does TI provide a complete configuration file for setting up the ADC32RF45 to produce a RAMP pattern in DDC bypass mode?
Kind regards,
Francois Tolmie