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ADS1299: Power sequence

Kuramochi Tadahiko
Guru 28715 points
Part Number: ADS1299

Hi,

If RESET is not released, is power(AVDD/AVDD1/DVDD) sequence free?

For example, is below power sequence no problem?

Best Regards,

Kuramochi

  • 0
    TI__Guru 66406 points
    Hello Kuramochi-san,

    Thank you for your post.

    Yes, it is ok to allow for the power supplies (AVDD and DVDD) to ramp up while /RESET remains low. However, the POR counter will not begin until /RESET is released and CLK is applied.

    VCAP1 will begin to ramp as soon as /RESET is high. The tPOR delay remains the same - you must wait for VCAP1 >= 1.1 V and 2^18 tCLK periods, whichever is longer.


    Best Regards,
  • 0 in reply to Ryan Andrews
    Guru 28715 points

    Hello Ryan-san,

    Thank you for your answer.

    I have an additional question.

    On the "7.3 Recommended Operating Conditions" of the datasheet, Analog to Digital Supply is specified "2.1V~3.6V".

    Is this valid after releasing reset?

    I would like to know if below condition is problem.

    Best Regards,

    Kuramochi

  • 0 in reply to Kuramochi Tadahiko
    TI__Guru 66406 points
    Hello Kuramochi-san,

    The condition you described is not a problem during power-up. The Recommended Operating Conditions list the device configuration settings to achieve typical ADC performance. The spec "-2.1 V < (AVDD - DVDD) < 3.6 V" only applies to normal operation. As you can see in the Absolute Maximum Ratings table, we do not give a similar spec; therefore, there is no concern with damaging the device if DVDD = 3.3 V and AVDD = 0 V.

    Best Regards,