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ADS8555: Reading of Control register of ADS8555 is not possible.

Expert 4445 points
Other Parts Discussed in Thread: ADS8555

art Number: ADS8555

Hello team

The following question came from a customer to Japan CSC.

I set Control Register in 0x0043 03FF.

C22 A-NAP:1 = Auto-NAP feature enabled
C17 READ_EN:1 = Control register contents output on SDO_x with next access
C16 C23:0_EN:1 = Entire control register update enabled (serial mode only)
Bit except the above is a default value.


Value becomes 0x7FFE 7FFE when I read a value of CR in the following procedures.

Procedures:
①With FS as Low, I send SCLK for 96bit.
②value of SDO becomes value unlike 0x7FFE 7FFE.

(I attach a wave pattern of SCLK,SDI,SDO at that time.)


Please tell me the right procedure to read a value of CR.

For example, with CONVST_A as High, BUSY becomes High and becomes Low.
At that time, is a value of CR readable from SDO_A if I input SCLK 32?


Best regards,
Keishi,Nishijima

Japan CSC


  • Hello Keishi-san,

    I'm looking into the detail and will get back to you soon, thanks.

    Best regards

    Dale

  • Hello Keishi-san,

    I have few question and suggestions after check the excel file:

    1. Can the customer get the correct out data without any change Control Register (default value)?

    2. Keep software mode at the end of Flow 1 until the end of Flow 2, and check the data on the SDO in Flow 2 again.

    3. Read the default value of Control Register after power up the device, check if it is 0x000003FF.

    Please let me these test results, thanks.

    PS:  By default configurations for input range without any change in CR, the input range for channel pair A/B/C is 4*Vref, so HVDD should be greater than 4*Vref  and HVSS should be less than -4*Vref, but the actual HVDD/HVSS in the customer's schematic is powered by +/-5V, which does meet the requirement, also notice that the performance specifications in ADC datasheet are specified for HVDD=10~15V and HVSS=-15~-10V test conditions.

    Best regards

    Dale