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ADC32RF45EVM: JESD204B Interface not working, No SYNC.

Michael Filkorn
Prodigy 50 points

Part Number: ADC32RF45EVM
Other Parts Discussed in Thread: ADC32RF45, LMX2582, ADC32RF42, LMK04828

Hello Everyone

I am using the AD32RF45EVM  with an Xilinx Virtex Ultrascale+ 9, 3e- Board to develop an JESD204B link to transfer the data from the ADC-Converter to the FPGA. Therefore i have implemented a JESD204B Receiver on the FPGA with the IP-Core from Xilinx( JESD204B v.7.2). The TX in this setup is realized by the JESD204B Interface of the ADC32RF45. Now i am having problems to establish a JESD link between the ADC32RF45 and the FPGA.

My configuration of the FPGA is : LMFS= 82820, K=16, Lanes =8 , Scrambling off, SYSREF not required, SYSREF always off, Line Rate = 4,096 GbpsQPLL1, drpclk= 102,4 Mhz, sample sysref on negative edge, LMFC Buffer =256, JESD204 with global clock. I am supplying the Core Clock and DRP clock separate from the Transceiver reference Clock, through DClkout12 with 102,4 Mhz..

My configuration of the ADC32RF45EVM is : Internal Clock of LMK4828 is 3072 MHz, Sample Clock of ADC is 1024 Mhz. LMX2582 supplies ADC clock.Reference Clock for the FPGA is ( DClkout0 =102,4 Mhz, Divider =30), SYSREF is 3,2 MHZ( Divider =960) and applied to ADC on SDClkout1 and on FPGA on SDClkout3 in continous mode. I am putting two lower frequency signals from an signal generator to both of the ADC input channel, with 12 Bit resoultion and in bypass mode.

The PLLs of the transceivers on the FPGA are already locked and the reset of the receiver is done. I also could achieve CommaDetermination ( gtCommaDet) for all lanes. Also i had read out through debug regsiters of  the Receiver that the RX had temporarily a SYNC High signal and CGS(Code Group synchronization) and also incoming K28.5 initialization characters I got the result oftemporarily(very short time)  SYNC/CGS when i was sending Link Layer Testmodes(continous K28.5 and Repeat ILA)  from the ADC GUI. But the Link has no permanent synchronization, but in the HDL-Simulation of the JESD204b Rx everything is working fine with permanent sync and sucessfull data transmission.But in the real system no permanent SYNC was seen and no data was received at the FPGA.

I would be happy if you could help me with this issue !

Regards

Michael

hereby i am sending you my configuration file of the ADC32RF45 EVM GUI

Michael_LMFS8280.cfg

  • 0
    TI__Expert 4880 points
    Michael,

    I have forwarded your question to a device expert. They should be with you shortly.

    Yusuf
  • 0 in reply to Yusuf%20Agoro
    TI__Expert 3515 points

    The minimum sampling clock frequency for this device (ADC32RF45) is 1500MHz. Consider using ADC32RF42 if you want to clock it at 1024MHz. 

    Satish.

  • 0 in reply to Satish Uppathil
    Prodigy 50 points

    Hi Satish

    Thank you for your help and your fast reply. I changed the sample clock and the parameters on the FPGA to double the original values . Sample Frequency is now 2048 Mhz, with refernce clock = 204,8 Mhz. I am delivering the clock to the ADC from the LMX2582. In the case of 2048 Mhz i set the seg 1 divider to 3 to deliver 2048 Mhz to the ADC, from whcih the ADC directyl samples in bypass mode without DDC .

    How does the Clocking for the JESD204B Interface on the ADC32RF45 works ? How to select the right frequency ?

    Actually i am getting permanent SYNC high and CodeGroupSynchronization(DebugRegsiters on FPGA)  now with the new design , but its only high wenn sending K28.5 Characters Link Layer Test Mode and no ILA happens then. With the normal ADC data as Link Layer Test Mode the SYNC never goes high. I am sampling a signal from both ADC Channels with 2024 Mhz sampling rate.

    How can i achieve a permanent SYNC high and Initial Lane Alignment and Data Transmission in the normal ADC mode  ?

    Regards

    Michael

    Michael_2_LMFS8280.cfg

  • 0 in reply to Michael Filkorn
    TI__Expert 3515 points

    Hi Michael,

    Are you using the EVM GUI to program the ADC? If so, have you tried configuring using the quick start tab of the GUI.

    The JESD clock in the ADC is derived (from the sampling clock) internally based on the mode chosen. Do you have our capture card (TSW14J56) to verify the programming sequence? 

    Regards,

    satish.

  • 0 in reply to Satish Uppathil
    Prodigy 50 points

    Hi Satish

    I am using the EVM GUI to configure the ADC and the LMK04828 and the LMX2582. Also i tried to use the Quick Start Button : But it didn't get the system running and the JESD204B synchronizing permanently. The EVM user guide also provides little information about setting up the system. I am trying to configure teh EVM GUI in many different ways ,a lso with the example configuration files provided by TI, but i couldnt get the system working since weeks.

    Could you propose me a way to configure teh ADC EVM GUI to correctly run teh system and achieve JESD204B SYNC hig ?

    I have no TSW14J56 Card and i wont be able to buy one. I am debugging the system by readout of several debug registers and signals from my FPGA Board.

    Regards

    Michael

  • 0 in reply to Michael Filkorn
    TI__Expert 3515 points

    Hi Michael,

    The GUI's quick setup tab should be enough to configure the device in 82820 bypass mode. Can you re-start the GUI, make the selections highlighted in yellow in figure below and click on the "program evm" button? You can choose "internal clk freq" another value if needed.

    Once you do this, the GUI should show the JESD204b settings as shown in the box circled in blue. Current consumption should be >2A. Or have you already tried this?

    Regards,

    satish.

  • 0 in reply to Satish Uppathil
    Prodigy 50 points

    Hi Satish

    I set up a new design with full sampling rate of the AD32RF45 at 3 Gsps at 12 Bit and changed all values. The old 2 Gsps solution works unstable and only sometimes gets SYNC high and data transmission. The new 3 Gsps solution works also sometimes but in all cases. If i get a working system , i can restart the FPGA and the interface is still connecting and synchronizing again and also data is sucessfully transmitted. However the Problem is in theconfiguration of the ADC EVM Board. If i once got a right configuration of the ADC Board through the GUI all is fine. But if save that configuarion of the ADC  board as an config(cfg.) file and restart the system with with the "conservated" config file and not through the GUI.  The system doesnt work with the loaded config file. Also the power consumption is 11.67 W with the loaded config file and 12.92 W in the manually configured system, while the config file was saved as a copy of the manually configured  working system with 12,92 W.Also it it is always necessary to toggle SYNC Polarity to sucessfully run the system.

    Which box and figures you mean ? I dont see any in your post

    How to achieve a sucesssfully and repeatable working configuration of the ADC EVM Board ?

    Regards

    Michael

    Hereby i send you my config file, which is an image of the working configuration at 3 Gsps.Michael_LMFS8280-3G_1.cfg

  • 0 in reply to Michael Filkorn
    TI__Expert 3515 points

    Hi Michael,

    The GUI configures the EVM by loading the relevant config files from its library. And that is stored in the following location: C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM GUI\Configuration Files\

    You'll find the config file it loads in the above folder and the file names are descriptive (with corresponding LMFS). I will suggest using these files if you want to load a config file, rather than using the GUI quick setup tab. You'll also have to load the relevant files to configure LMK and LMX chips. And the sequence of configuration should be: LMK, LMX and then ADC.

    As an example if you want to configure the ADC at 2949.12Msps and want to clock that with LMX, you'll have to use the following files in sequence:

    C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM GUI\Configuration Files\ADC32RF45\Bypass DDC Mode\LMK_ADC32RF45_bypass_2949Msps.cfg

    C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM GUI\Configuration Files\ADC32RF45\LMX_2949p12M.cfg

    C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM GUI\Configuration Files\ADC32RF45\Bypass DDC Mode\ADC32RF45_82820.cfg

    The ADC configuration requires a specific sequence of register writes which is broken when you use the read back values to re-configure. It also breaks the above sequence (LMK, then LMX and then ADC).

    Its not required to toggle sync polarity. The polarity set in the ADC and FPGA just have to match. You will see a register write to invert this in the ADC config file and you can remove it to avoid the toggle.

    I was referring to the box in quick setup tab of the GUI where it shows the LMFS setting, but somehow the picture didn't get attached. But, I think you're now already familiar with it.

    Regards,

    satish.

  • 0 in reply to Satish Uppathil
    Prodigy 50 points
    Hi Satish

    Thanks a lot for your help and your time. I tested a lot with the ADC Gui and found a way to programm the ADC , so that the JESD204B Interface works. I configured the registers otherly because i use clock 12 of the LMK for my FPGA logic design. Now it always synchronizes with my Configuration and i wrote myself a guide to configure the ADC System. But it works only with the 3 Gsps / 307,2 Mhz design only and not with 2 Gsps/ 204,8 Mhz, which is ok for our application.

    Regards

    Michael