Other Parts Discussed in Thread: LM3S6965, ADS1278, ADS8365, ADS8556, ADS8361, ADS7953
I've just decided to use the ADS1278 for a general A/D module together with a Stellaris Cortex M3 (LM3S6965). I just ordered the ADS1278-EVM to get kick started, but I can't wait for it to arrive before getting answers to a few questions:
1. Protocol
Guess i'm pretty new to the frame-sync protocol, while I haven't interfaced too many ADCs in my days (although a load of other circuits). I figure I need to use the frame-sync protocol, since I'm planning on squeezing the highest sample rates available from the chip (where SPI isn't available, as far as I understand). I've looked around, and I can't find a more explicit definition of the protocol than in the device datasheet. Is there an appnote, or such, where I can find more details of the frame-sync features? Any hints on how to implement frame-sync-protocol on a Cortex M3? Is it a go to start with hardware SSI module, or am I rather going for interrupt-driven bit-banging?
2. Synchronization
In one application, I need to synchronize sampling to external events (<= 54 kHz), rather than to fixed time. After reading through the device datasheet a couple of times, the best solution I figure would be to clock the ADC with a high constant clock rate (f_clk), and keep pulling ^SYNC-pin to get the samples done at the right moment. HOWEVER, what I can't really figure out is the sync. timing, although plenty of graphs tell me the numbers in the datasheet (page 28). Will it really take up to 129 conversions between one synchronized sample and the time I can read the data? Does this mean that I can only sample the best of one 129th of the maximum rate if I'm going for synchronized event sampling? I really hope I have gotten this interpretation wrong, perhaps does it mean 129 t_clk's, which would more correspond to half normal sampling period?
Thanks in advance for replies!
- Stefan