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ADS1281: Questions (Data rate vs clock freq., settling time when MUX'ing, & 24-bit output format)

Dean Palmer
Prodigy 50 points
Part Number: ADS1281
Other Parts Discussed in Thread: ADS1282

I have a few questions about the ADS1281 Analog to digital converter:

  1. Table 5 specifically says the rates provided are for a 4.096 MHz clock.  Table 6 doesn't explicitly state that.  Should we assume that the rates in Table 6 are for a 4.096 MHz clock and scale them accordingly when we use a slower clock, or are they absolute?
  2. Is there any kind of pipe-lining in the output stream?  We have a mux before the input to the ADC and are having some timing issues.  We understand that the FIR output requires 63 cycles to settle after we swtich the mux.  (We are running in Continuous-Sync Mode.)  Does that mean we need to wait for 63 DRDY pulses or is that delay already included?  When is the best time to swtich the mux?
  3. How do we set the device for 24-bit output data?

Thanks,

--Dean Palmer

  • 0
    TI__Mastermind 44680 points

    Hi Dean,

    Welcome to the TI E2E Forums!

    To answer your questions..

    1. The decimation ratios are absolute; however as you pointed out, the data rates will scale with the fCLK frequency.

    2. There is pipe-lining only in the sense that as soon as a conversion completes, the ADC will begin a new conversion right away, meanwhile the calibrated conversion result is computed and /DRDY goes low while the ADC is performing the next conversion. However, since this is a multiplexed ADC, there is only a single delta-sigma modulator and digital filter; therefore, it is not possible to perform any kind of simultaneous or concurrent sampling of both input channels.

      When re-configuring the ADC (changing the MUX, for example), the digital filter and all its taps are reset. The previous conversion is halted and a new conversion begins. Therefore, the settling time will be the full 63-conversion periods for the filter taps to acquire enough data to compute a "settled" result.

      NOTE: If you use the SINC5 filter, then the digital filter settling time will be approx. 5 conversion periods instead of 63 conversion periods with the FIR flat-pass band filter.

    3. There is not a 24-bit data mode per se... There is a modulator bitstream mode, or 31-bit filter data mode (the 32nd bit is a redundant sign bit). You can, however,  clock out the first 24-bits of data and stop the SPI communication after that if you are only interested in 24-bit data.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 50 points

    Chris,

    Thanks for the answers.  I have a few follow-ups:

    1. That is what we observed.  I guess I was just trying to point out that Table 6 was not clear about that.
    2. Note that we are using the ADS1281 which does not have an internal mux.  We are using an external mux.  We do not reconfigure the ADC during operation.  Also, we are using Pin Mode configuration so our filter options are limited.  (We can't configure for Sinc filter only.)  So, if I understand correctly, after we change our external mux address, we need to wait for 63 DRDYs to go by to allow the data to settle.  Is that correct?  If we are using the 250 FIR DATA RATE from Table 6, that would take about 252 msec.  Is that correct?  (By the way there are places in the data sheet which indicate settling time is 62 Fdata cycles and other places where it indicates 63.  Can you explain the difference?)
    3. I figured that out while waiting for your response.

    Thanks for your help,

    --Dean

  • 0 in reply to Dean Palmer
    TI__Mastermind 44680 points

    Hi Dean,

    1. OK. I've made a note of this to update in a future datasheet revision.

    2. My mistake, I was thinking of the ADS1282 with the internal multiplexer.

      Do you have the ability to control the /RESET pin?
      After switching the multiplexer you could toggle the /RESET pin (it acts as the SYNC pin in PIN controlled mode) to restart the ADC conversion. By doing this you would  would still have the tDR (~63) conversion period delay. However, by restarting the conversion, the /DRDY signal would remain high until the digital filter result was settled.

      Without synchronizing or re-starting the ADC's conversion you would need to count and wait for 63 conversion periods (Yes, 252 ms for the 250 SPS data rate)  so that digital filter's output data represents the current MUX channel.

      The precise time from a synchronization to when /DRDY goes low is given in table 11 as 62.98046875/fDATA + 468/fCLK, so this is effectively 63 conversion periods. I know that some of this settling time is due to digital delay other than the digital filter, but I'll have to look into it to determine how much.
       

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 50 points
    Thanks, Chris. We don't currently have a way to control the /Reset pin. We will keep this in mind though.

    --Dean