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DDC118: CONV toggle timing acceptable range

Don Foong
Expert 4100 points

Part Number: DDC118
Other Parts Discussed in Thread: DDC264

Hi Team.

My customer is using DDC118 for light sensing application. For improving EMC noise radiated from the 16MHz clock line, they have to change it to 4MHz, which is supported by DDC118.

From page 9 of the datasheet - it is recommended “For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended that CONV toggle within ±10ns of the rising edge of CLK.”

Upon changing MCU control clock to 4MHz, it could only achieve best time of ~12ns (CONV toggle time relative to the  rising edge of CLK) due to the limit of the MCU. Please advise is 12ns within the acceptable range for DDC118 ?

Look forward to your feedback, thanks in advance.

 

Regards,

Don Foong

 

  • 0
    TI__Genius 12025 points
    Hi Don,
    How are you?
    Thank you for helping the customer using DDC118 device.
    We will look into the customer's question and
    will reply to you very soon.

    Thank you very much!
    Have a very nice day!

    Best regards,
    Chen
  • 0 in reply to Chen Kung
    TI__Expert 4680 points

    Hi Don,

    This device was released long ago so it is hard to find much clues... The designer believes that the concern was that when CONV changes away from the CLK rising edge then for a fixed CONV period you may end up with the internal number of clks fluctuating by +/-1 clk per integration.  Every clk edge contributes a small disturbance and if the number of those edges changes one would end up with small, sample to sample differences.

    Also, I kind of remember that in the newer devices like the DDC264 this was actually not respected in the EVM and the CONV edge could match a rising or a falling edge of CLK, depending on power up/FPGA start-up. When that happened there was no noticeable difference in performance. Nevertheless, these are newer devices and the effect described above could be no issue on them while they may be for the DDC118. So, we can't tell 100%. My feeling is that I doubt customer can see the difference of using 12ns instead of being within 10ns, but the only way for them to know is to try it out... 

    Regards,
    Edu

  • 0 in reply to Eduardo Bartolome
    TI__Expert 4100 points

    Hi Edu,

    Thanks for the feedback. We will communicate with customer and advise them to try out and take note of any noticeable differences compare to running at 16MHz.

    Regards, Don

  • 0 in reply to Don Foong
    TI__Expert 4100 points
    Hi Edu,

    Our customer had tested on one unit, the changes from 16MHz to 4MHz work very well. It does not show any significant reading variations even with 12ns delay between CONV and CLK.

    Apart from the comparing the readings, customer like to know is there any better checking method to verify the 4MHz clock is working well ? Any suggestion ?

    Thanks again for the help.

    Regards, Don
  • 0 in reply to Don Foong
    TI__Expert 4680 points

    Hi Don,

    Beyond what they did, I can only think of doing some kind of characterization under those conditions. Of course, that can be very extensive work (imagine recheck the whole datasheet), so, maybe, the most sensitive test that would flag a problem would be to run linearity. That may not be so easy, though, if they don't have an accurate source and/or meter. Basically the test is done by connecting a voltage generator to a large resistor (say 10MOhm) in series with the input. The input can be considered ground and as such, this configuration injects a known current into the device (except for a gain error introduced by the tolerance of the resistor). If one doesn't have a precise source, they can always measure the voltage with an accurate meter (notice that we are talking about 20bit devices...). The normal way then is to take few measurements at different amplitudes, fit a line and see that the device meets linearity specs. The math may not be as straightforward as it sounds, though... Again, not an easy test for someone not so familiar with the device.

    A simplification of this would be to simply do a spot check at one amplitude. I.e., do what they did but applying a signal as described above and see that there are no significant variations between readings... Maybe they did that already?

    Regards,
    Edu

  • 0 in reply to Eduardo Bartolome
    TI__Expert 4100 points

    Hi Edu,

    Thanks for the feedback and support.

    Regards,

    Don