• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 48 subscribers
  • Views 525 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12DJ3200EVM: none

Zachary Dryer
Prodigy 135 points

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: LMK04828, LMX2582, ADC12DJ3200

Is there a document that specifies the bit pattern of each Jmode on the ADC? I know about the information on the datasheet but I can't find what S0 or A0 and B0 are in bits.

  • 0
    TI__Mastermind 44680 points

    Hi Zachary

    That information is described in section 7.4.3.1 JESD204B Output Data Formats and 7.3.5.3 Output Data Format

    12-bit real Sn, An, Bn are xxxx xxxx xxxx offset binary or signed 2's complement.

    8-bit real Sn, An, Bn are xxxx xxxx offset binary or signed 2's complement

    15-bit real or complex An, Bn, AIn, AQn, BIn, BQn are xxxx xxxx xxxx xxxx where the least significant bit contains Over-range information as shown in Tables 13 and 14.

    Information is always organized as MSB first (earliest octets, left-most in the data mapping tables) and LSB last (later octets, right-most in the data mapping tables).

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 135 points

    The ADC12DJ3200EVM has onboard clocking solution but I cannot find any documentation on it. What is the clocking rate for the onboard configuration? Specifically is there a clock rate for Jmode11? We are wanting to connect this to ZCU Ultrascale+ FPGA dev board using a sample Fs rate =  3200Msps. Are there any more considerations with these details?

    Let me know.

    Thanks,

    Zach

  • 0 in reply to Zachary Dryer
    TI__Mastermind 44680 points

    Hi Zach

    The board architecture uses PLL1 of the LMK04828 to generate 100 MHz using a VCXO. This can be optionally frequency locked to a 10MHz reference applied to CLKIN0.

    The 100 MHz reference is used by the LMX2582 to create the ADC sampling clock, and a same frequency clock which drives the LMK04828 output path circuitry in distribution mode.

    By default in JMODE11 with 3200 MHz to the ADC12DJ3200 and to the LMK04828 distribution path, the following clocks are output to the FMC:

    SYSREF to FPGA is at 20 MHz from LMK04828 SDCLKOUT1 and is output on FMC pins G9/G10.

    CLK1 to FPGA is at 200 MHz from LMK04828 DCLKOUT0 and is output on FMC pins D4/D5. The divider for this output is at address 0x100h bits 4:0.

    CLK2 to FPGA is at 200 MHz from LMK04828 DCLKOUT12 and is output on FMC pins G6/G7. The divider for this output is at address 0x130h bits 4:0.

    CLK3 to FPGA is at 200 MHz from LMK04828 DCLKOUT8 and is output on FMC+ pins Z20/Z21. The divider for this output is at address 0x120h bits 4:0.

    All of these frequencies will scale with the ADC clock frequency if you use something other than 3200 MHz.

    If you need different FPGA CLK frequencies for the ZCU board you can adjust the divider settings in the following configuration file: LMK04828_JMODE11.cfg

    The configuration files should all be in this folder: C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\Configuration Files

    Best regards,

    Jim B