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DAC8734: DAC 8734 READ

man young kim
Prodigy 40 points
Part Number: DAC8734 
*DAC 8734 READ Questions*

1.Voltage on DAC 8734 READ
->The voltage used for DAC control is (DVDD (+ 5v) / IOVDD (+ 3.3v) / AVDD1,2 (VDD + 15v) / AVSS1,2 (-15v)).Of the four voltages, only DVDD + 5v / IOVDD (+ 3.3v) is supplied to the DAC.
In case of DAC READ, we ask if AVDD1,2 (VDD + 15v) / AVSS1,2 (-15v) should be applied to DAC.

2.Is the DSDO signal to be 1 when writing? If it is set to '1', should it be controlled to '0' when it is read and read?

3.Resister map for DAC when wirte

(x"00" x"0080") DSDO : '1' 

(x"04" x"4000")


Resister map to DAC when read

(x"84" x"0000")


Write to dac on 24bit 1cycle dac.

cs:       high -> low -> high

clk:      low -> 24clk -> low 

data     low -> 24data ->low


If read, should CS be applied to dac for 2 cycles? E.g

cs:       high -> low -> high -> low-> high

clk:      low -> 24clk -> low -> 24 clk->low

data     low -> 24data ->low-> 24data -> low 

thank you

  • 0
    TI__Mastermind 46290 points

    Hello Man,

    man young kim said:
    In case of DAC READ, we ask if AVDD1,2 (VDD + 15v) / AVSS1,2 (-15v) should be applied to DAC.

    From previous experience with similar devices, a read operation should be possible with only IOVDD and DVDD applied. In fact, the power supply sequence suggests that IOVDD and DVDD are provided prior to AVDD and AVSS.

    man young kim said:
    2.Is the DSDO signal to be 1 when writing? If it is set to '1', should it be controlled to '0' when it is read and read?

    This is not required.

    man young kim said:
    If read, should CS be applied to dac for 2 cycles? E.g

    Yes, it takes two full frame cycles to complete a read sequence. This is illustrated in Figure 3 on Page 11 of the datasheet.

    Hope this helps!