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ADS1278: McAsp interface on AM335x

Quim
Prodigy 20 points

Part Number: ADS1278

I would like to interface the ADS1278 with the AM335x. According to the section 22.2 the AM335x has two instantiations of the McASP subsystem: McASP0 and McASP1. Each of one with 4 serializers AXR[0:3]. The ADS1278 however has 8 channels. I want to use the max data rate (144kSPS), if possible, trying to avoid TDM mode, using instead Frame-Sync discrete mode. My question is, if using an external oscillator to feed both McASP0 and McASP1, can I "merge" them to use the 8 channels in parallel, i.e., 4 channels for McASP0  and 4 channels for McASP1 ? Or the only way is using TDM mode?

Thank you in advance.

  • 0
    TI__Guru 69456 points
    Hello Quim,

    Thank you for your post and welcome to our forum!

    We cannot give much insight into your microcontroller's capabilities since we're not the experts there. It sounds like, if you are sharing the same FSYNC and SCLK between the two McASP peripherals, then you could theoretically read 4 channels with one and the remaining 4 channels with the other. The only thing you'd need to figure out is which peripheral acts as the master and which one acts as a slave. You don't want both peripherals trying to drive FSYNC and SCLK to the ADS1278.

    I'm not sure what you mean by "sharing an external oscillator" with McASP0 and McASP1. The external oscillator should be the master clock input to the ADS1278, which controls the conversion rate.

    Otherwise, TDM mode should work just fine, as long as your SCLK is fast enough to ready 8*24 bits within each frame.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 20 points
    Hi Ryan,

    Thank you very much for your quick response.

    1.Just to double check I understand what you propose. A possible scheme could be:

    McASP0 (master):
    Master clock from external clock (37MHz)
    FSYNC generated
    SCLK generated
    Channel[0:3] from ADS1278

    McASP1 (slave):
    FSYNC from McASP0
    SCLK from McASP0
    Channel[4:8] from ADS1278

    ADS1278
    CLK from external clock
    FSYNC from McASP0
    SCLK from McASP0


    2.The ADS1278 requires a 37MHz master clock for high speed . The AM335x can create this clock internally, but the max frequency is 26 MHz (from my understanding). However the master clock can be supplied from an external oscillator. The idea would be feed McASP0, McASP1 and ADS1278 from the same external oscillator. This is what I mean with "sharing an external oscillator".

    3.For TDM mode, if working at high speed, SCLK and CLK could be the same, that is, 37MHz. From what I have read it is necessary to use a flip-flop to re-clock. A part from that and assuming I use this flip-flop, do you see any problem from working at 37 MHz in TDM mode?

    Thank you again.
  • 0 in reply to Quim
    TI__Guru 69456 points

    Hi Quim,

    Yes, scenario #1 is correct. In a Frame-Sync Interface, the master clock and frame signals must be synchronized such that there are an exact number of clock periods in each frame.

    The flip-flop becomes necessary when the MSB propagation delay is longer than the SCLK period (see image below). As long as you have accounted for this, I do not see any other issues with TDM Mode at full-speed.