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ADC12D1600: pin-package delay

Part Number: ADC12D1600

Hello,

Is there information available with respect to pin-package delays of the ADC12D1600CIUT?
I want to use this information for the PCB layout to minimize the skew between the LVDS lines (clock and data).

Kind regards,
Heino

  • Hello Heino
    We don't have detailed pair by pair timing information available for this device, but systematic skew is quite low between data and DCLK pairs.
    Our standard recommendation is to route all data and DCLK signals with matched delay.
    Best regards,
    Jim B