Hi,
I have found a very strange behavior of my custom AFE5809 board.
The ADC_clk is 20MHz, decimation factor M=32, output bit number is 16. Moudle bypass = 0, output channel select = 0 , full LVDS = 0, so that A.I, A.Q, B.I and B.Q will come out on lane 1 sucessively, followed by 28 padded zeros. I will only have to retrieve data on lane 1/3/5/7 for all the 8 channels.
To my through, these 4 lanes should be all syncronized to FCLK, but actually it is not in my case. Please see Figure 1. Although lane1 and lane 3 are syncronized, there is a random delay between lane 5/7 and lane 1/3. When I say "random", I mean the delay is different after every system reset, but will not change after then.
Figure 1 : data on the 4 lanes after serial to parell transorming, sample clk = 20MHz
To make sure whether this delay is introduced by my FPGA logic, or by 5809 it self, I then observed the data before serial to parell transorming, which is shown in Figure 2, and is in consistence with Figure 1. so I guess the delay is from 5809.
Figure 2 data on 4 lanes before serial to parell transforming. sample clk=80MHz (under sampled, but ok for demonstrating)
The problem is how dose this delay come? this makes the FCLK meaningless. What should I do to avoid such delay? Thank you!
