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ADS1278 Supply Start-up Sequence

KAL CONLEY
Prodigy 40 points
Other Parts Discussed in Thread: ADS1274, ADS1271

Howdy Folks,

How important is the supply startup sequence for the ADS1274/8. Can improper sequencing cause the ADC to malfunction? If so in what ways? Will the device eventually recover? Start-up time is relatively unimportant in our design. We are trying to minimize component count and would like to avoid having to sequence all three supplies, if possible. Is it more important to sequence AVDD last than it is to sequence IOVDD after DVDD? I noticed that the ADS1274EVM uses the TPS73018 to supply DVDD from IOVDD. I take it, that the delay caused by the TPS73018 will make DVDD sequence after IOVDD? This leads me to believe that the IOVDD DVDD sequence is unimportant. Could somebody shed some light on these issues?

Thanks,

Kal

  • 0
    TI__Mastermind 43915 points

     

    Hi Kal, 

    Powering up the device in the wrong start up sequence will not damage the device. The reason it is stated to use the sequence DVDD then IOVDD and then AVDD is so the part will function properly with steady currents. Once the ADS1274/8 is powered up with AVDD, it looks at the digital voltage to configure itself and set default data (the ADS will then know if it is a 4 channel or 8 channel part, what speed mode to run in…. Etc). If the AVDD is powered up first, it will look to the digital pins and see that they are floating. It will then power up in some unknown state until the digital voltage is supplied. However, once the digital voltage is supplied, it will work correctly. It is just important that all the supplies are provided.

    The supply ramp rate is just something to keep in mind. It does not effect the operation of the part and there is not a certain rise time that is required. Make sure that when the supplies are turned on they do not spike to a large value, risking damage to the part. 

    Regards,

    Tony Calabria 

     

  • 0 in reply to Tony Calabria
    Expert 2600 points

    Hi Tony,

     

    thanks, have the same problem now.

    Is there a recommended circuity for that?

    The ADS1271EVM_PDK should contain something, but I can't find the schematics.

    Thanks for helping

     

    With best regards

     

    Gerhard

  • 0 in reply to Gerhard Kreuzer
    TI__Mastermind 43915 points

    Hi Gerhard,

    Are you having a problem following the supply sequence or a problem with the ramping time?

    For the supply sequence - Make sure you have the 5V to the MMB0 powered before the high voltage (+/-10V) supplies come up. The high voltage supplies power the driving amplifiers while the 5V is used for the MMB0 to regulate all the necessary supplies for the ADS1271 chip itself. If you power the high voltage supplies first, there is a chance the driving amplifier will be providing a voltage to the input of the ADC before the ADC is powered. This is something that you want to avoid. If you are not using the MMB0 and are having trouble controlling the sequence of the AVDD and DVDD, you can use the J6 jumpers to control when you power one supply versus the other. 

    For supply ramp time - Simple solution would be to add some bulk capacitance to slow down the ramping time. We have found adding 10uF+ on the power supply will slow the ramp significantly and help due away with transients.

    When it comes to designing your own board - a common design practice is to use on board regulators and use the same supply to power these to make sure the supplies all come up at once. This is the technique we use on the MMB0 motherboard to create the DVDD from the AVDD.

    Let me know what other questions you have and I will be happy to answer them.

    Regards,

    Tony

  • 0 in reply to Tony Calabria
    Expert 2600 points

    Hi Tony,

     

    thanks for the reply.

    You were right, I starting off my own design. Ok, I will use a higher voltage rail and connect the regulators for AVDD and DVDD there. The output of all this regulators get some low ESR capacitors in parallel and having together something about 20µF. Hope that works in all circumstances ..

    I will use standard LDOs, I found types with two LDO's in a single package, but without any interconnection, like sequence control or something like this.

    I also will vary the value of the capacitors, so the first supply get the weekest and the last supply (in the time domain) gets the greatest ... (not vice versa). A little detail, but it maybe important.

    The sequence for powering off the device will also be DVDD first and AVDD last when using capacitors, hope this isn't a problem.

    With best regards

     

    Gerhard

     

     

  • 0 in reply to Gerhard Kreuzer
    TI__Mastermind 43915 points

    No problems with that power down sequence.

    Caps will help with the ramp times so you should be alright.

    Let me know if you have any other problems.

    Regards,

    Tony

  • 0 in reply to Tony Calabria
    TI__Expert 8705 points
    Hi,
    So the power sequence could be not needed, right?
    If it is still needed, what is the delay between each power rail up? The datasheet doesn't state it. Thanks.
  • 0 in reply to Wayne Liu
    TI__Guru 66186 points
    Hi Wayne,

    The datasheet says to bring DVDD up first (or at the same time as IOVDD), then AVDD. This is just to ensure that the device will power-on in a known good state, but you will not damage the device otherwise and there is no strict timing requirement. The 3 supplies are "ANDed" together to generate a global power-on reset. You can always issue an additional /SYNC pulse to restart conversions after power-up to ensure consistent performance.

    Best Regards,