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DAC37J82: DAC37J82

Thang pham
Prodigy 20 points

Part Number: DAC37J82
Other Parts Discussed in Thread: DAC38J84, DAC38J82

So I'm trying to understand the datasheet of the DAC37J82.   Table 3 in section 7.3.3 It talks about the relationship between lane rate and SerDes PLL output clock frequency.  The table also has a column RATE which contains Full, Half, Quarter, and Eight.  What is rate in this column referring to?  Also, what is the relationship between these rate and the input sample rate and/or the number of lanes used.

Also, register  0x22 (config34) contains path select for input PathA,B,C,D and output PathA,B,C,D.  There is no where in the datasheet that I can find anything that discuss about these paths.  As far as I can tell, there are only 2 input paths (from Functional block diagram on page 23) that are coming from the JESD204B interface before they go into the Input Mux block.  

Appreciate any clarification on these. 

Thank you!

  • 0
    TI__Guru* 91947 points

    Thang,

    The two upper bytes of address 0x22 control the input data mux which is sending data from the JESD Block to the NCO/Mixer/Dither digital Block. The lower two bytes select how the digital block output data is routed to which DAC. In the case of the DAC38J82, data can be routed to any of the four available DAC's but only two of them. In the case of a DAC38J84, data can be routed in any desired order to all four of the output DAC's. 

    For your first question take a look at the attached document.

    Regards,

    Jim

     6303.DAC38J84 Clock, PLL and SERDES Configuration.docx