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AMC7836: About AMC7836

Vera Mao
Expert 5065 points
Part Number: AMC7836

Hi dear supporting team,

for AMC7836, which has SPI connect to FPGA,  if below scenario happens:

1) if IOVDD =0V, and AVEE\AVSS_B/C/D floating, what's the possible consequence? such as damage?  will the DAC output voltage initial value be abnormal?

2)  if originally 7836 has normal power supply, but during the operation, the power supply abnormal(i.e. IOVDD=0, and DVDD、AVDD, AVCC_AB, AVCC_CD and AVEE\AVSS_B/C/D which connected to -08V is floating), will DAC output keep the original value when it was normal? 

3)because connect to FPGA, they sometimes will find signal re-filling(i.e. FPGA drive SPI signal to high),  customer tyed to increase the serial resistor to decrease current,  how much current should it be to avoid damage 7836?

TKS A LOT!

  • 0
    TI__Mastermind 46290 points
    Vera,

    Sorry about the delays on this topic. Paul should be able to give you an update today. Otherwise I'll check in again on this tonight.
  • 0 in reply to Kevin Duke
    TI__Guru 53773 points

    Hi Vera,

    1. If the VSS supply is floating and the device is reset, you can expect a small negative offset on the DAC outputs.  Any current flowing out of the DAC pins will activate the ESD cells, so you could expect about -0.7V on the output.

    2. If the supplies collapse the device will reset, and should be clamp mode, where the outputs follow VSS.  As VSS is now floating, you can expect about -0.7V on the outputs.

    3.In this case, I think you mean that the SPI lines are driving the IO pins before the IOVDD is established? If that is the case, then some series resistance, maybe 100ohm should help limit the current. If possible, IOVDD and the FPGA supply should be the same, which will help prevent this case.

    Thanks!

    Paul

  • 0 in reply to Paul_Frost
    TI__Expert 5065 points

    Hi Paul,

    thank you very much for your support!

    I may need add some more description on the issue to double check with you:

    scenario #1: when IOVDD has no power supply(i.e IOVDD=0),  and AVEE/AVSS_B/C/D which originally connected to -8V is floating,  but DVDD,AVDD and AVCC_AB, AVCC_CD are all with normal supply, there are two kind of situation:

    1) customer's brd may have above issue when powering up,  what's the influence to the reliability of 7836?  and how about the DAC output voltage?(they are afraid there is high abnormal voltage output which may burn other chip)

    2) all the power supply are normal originally, but due to some reason above power issue may happen, what's the influence to the reliability of 7836, and how about the DAC output voltage?(they are afraid there is high abnormal voltage output which may burn other chip)

    scenario #2:  IOVDD has no power supply (i.e. IOVDD=0), but AVEE/AVSS_B/C/D is connected to GND, and DVDD,AVDD, AVCC_AB&AVCC_CD is supplied with normal voltage,  there are still two situation : 

    1) customer's brd may have above issue when powering up,  what's the influence to the reliability of 7836?  and how about the DAC output voltage?(they are afraid there is high abnormal voltage output which may burn other chip)

    2) all the power supply are normal originally, but due to some reason above power issue may happen, what's the influence to the reliability of 7836, and how about the DAC output voltage?(they are afraid there is high abnormal voltage output which may burn other chip)

    tks a lot!

  • 0 in reply to Vera Mao
    TI__Guru 53773 points
    Hi Vera,

    Scenario 1: It is important to note that if any of the supplies are disconnected, the part with be in clamp mode, where the DAC outputs are resistively connected to VSS.
    1) The highest potential VSS can be when it floating is about +.7V, as that is when the ESD protection diode is activated, but for that to happen, the DAC would need to be sinking current, which I think is unlikely. The output would certainly not be able to source any current, because the clamp resistor is only connected to VSS.

    2) This would not change.

    Scenario 2:
    1) In this case the device is still in CLAMP mode, with a resistor connecting the DAC output to VSS, or in this case, ground. If the load on the DAC output is drawing current, the output will go negative, as low as -0.7V, as that is when the ESD cell turns on. If it is sinking current, then the output would be positive.

    2) This would not change anything, the output will track VSS with the CLAMP resistor.

    Thanks,
    Paul
  • 0 in reply to Paul_Frost
    TI__Expert 5065 points

    hi Paul,

    thank you for the reply! so in conclusion,do you mean：

    1. for all the scenario above, AMC7836 will not be damaged.

    2. for all the scenario above, AMC7836 will not generate very big signal.

    correct? tks!

  • 0 in reply to Vera Mao
    TI__Guru 53773 points
    Yes, correct. See figure 32-35 in the product datasheet for plots of the behavior, with the different that these supplies are not really floating, so they do not have 0.7V offset.