TSW14J56EVM: Simulation doesn't work

Mhed,

Try the following to resolve errors shown in Model Sim RTL Simulation

1.       Please copy and replace the attached Verilog files- dec_data_capture_gz.sv, enc_data_gen_gz.sv & jesdcon204b_top.v in the following IP folder

\* path of the project*\J56\J56D_respin\Altera_JESD204B\jesd204b_refdesign\ip.

And replace trigger_module.v file from the following location

\* path of the project*\J56\J56D_respin\Altera_JESD204B\jesd204b_refdesign\syn\AVGZ_gen_jesd204b_120_SP2_external_memory.

Forward references- using a signal in logic before declaring the signal type(wire or register) is not allowed in Model Sim

Attached Verilog files have the declaration issues fixed, please replace them in respective folder.

2.       When Model Sim software runs, it auto-generates a .do file ‘jesd204b_run_msim_rtl_systemverilog.do’ (script file for Model sim to execute) in following location:

The file can be either VHDL or Verilog or System Verilog based

We need to edit the .do file, add a command to compile package file first before proceeding to compile other modules

Please add the following command in .do file in the top after the libraries for IP cores are declared

file Path: \* path of the project*\ J56\J56D_respin\Altera_JESD204B\jesd204b_refdesign\syn\AVGZ_gen_jesd204b_120_SP2\simulation\modelsim

Command to include: vlog -sv -work work +incdir+C:/TI_Bit/J56/AFE7444_1/J56D_respin/Altera_JESD204B/jesd204b_refdesign/src {C:/TI_Bit/J56/AFE7444_1/J56D_respin/Altera_JESD204B/jesd204b_refdesign/src/jesdcon_pkg.v}.

Change the file path in the command from C:/TI_Bit/ to the path where project is restored.

We generated system Verilog based .do file and verified the package related errors got resolved, but the suggested solution should work even if .do file is VHDL or Verilog based. To change from VHDL to Verilog or system Verilog, change the EDA Tool Settings Simulation format accordingly.

EDA Settings available in Assignments->Settings tab of Quartus.

3.       Launch Model Sim from Start Menu instead of running from Quartus and execute the .do file with the following command in Transcript window Command: do C:/TI_Bit/J56/J56D_respin/Altera_JESD204B/jesd204b_refdesign/syn/AVGZ_gen_jesd204b_120_SP2/simulation/modelsim/jesd204b_run_msim_rtl_systemverilog.do

Please correct the file path from C:/TI_Bit/ to the path where project got restored

Once the command gets executed, all the modules will be available under work library in Model sim, from there it can be added to Wave window for simulation.

Above steps should be helpful to get the RTL simulation working.

Regards,

Jim

Source Files.zip

Hi Jim,

Thank you for your answer.

However, there was change in our company, i don't work on this project anymore. But i've transmitted this subject to my co-worker who now wokks on this project. I hope your answer will help him.