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ADC128S102: How much speed can be achieved practically using ADC128S102 and how to set its clock frequency

Priyanka Pote
Prodigy 50 points
Part Number: ADC128S102

Hello,

we are using ADC128D102 for fast Multiplexed Data Acquisition system and we want to convert analog data coming from 64 x 64 matrix, samples that are coming from my multiplexed circuit is 1 mega samples per second on all 8 channels of ADC and i want to read this 1 Mega samples per second data using all 8 channels of ADC in 1 second and as per datasheet of this ADC128 it can sample 1 mega samples per second , but i am facing problem while reading data because i am not able to read 1 mega sample per second using all 8 channels of ADC.

please give me some suggestion on this that how can i able to read 1 mega samples of data per second coming from my system on all 8 channels of adc.

I have done some testing experiment on ADC128S102, so i was testing this ADC with raspberry pi and i took readings for 1MSPS samples on a single channel which took  almost 17 Sec , but as per datasheet ADC128 is able to sample 1MSPS samples per sec i.e. 1MSPS is a sampling speed of ADC128 with 16 Mhz of clock frequency,

So my questions are 1) How to achieve 1Msps of speed on single channel of ADC128 ? ,because as per my testing i got only 97646 samples per second which is less than mentioned in datasheet

                                  2) How much speed we can achieve per channel while using all 8 channels of ADC?

       3) How to set Clock frequency of this ADC to its Maximum Allowed Frequency which is 16MHZ in this case to achieve 1msps ?

       4) How to increase and decrease sampling rate of this ADC, if i want to decrease sampling rate to 500ksps what should i do?

  • 0
    TI__Guru**** 180931 points
    Hi Priyanka,

    Welcome to our e2e Forum! For Q1) please review section 7.4 of the ADC128S102 datasheet, paying particular attention to the second paragraph in that section. For Q2, you can still maintain a 1 MSPS throughput, but that would be 125 kSPS/CH. For Q3, see Figure 1 - /CS has to toggle initially, but it can be kept low with a continuous clock, this would be difficult to achieve with a standard SPI type interface. For Q4, change your SCLK speed - SCLK drives the conversion rate so 8 MHz would be 500 kSPS (single channel - 62.5 kSPS/CH with 8 channels).