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TSC2006

Teodor Neagoe
Intellectual 260 points
Other Parts Discussed in Thread: TSC2006, TSC2008

These questions have been posted by one of my customers a while ago. He never received an answer.

Here they are again:

The following questions are to help me to understand how behave the TSC2006 when  it’s throughput (batch delay) is faster than the rate at which the processor read the X/Y coordinates.   The Window CE driver that is available on the TI web site use the TSC2006 in that mode.

-          When the TSC2006 finish processing a new X/Y coordinate but the processor has not read the previous coordinate is the new coordinate overwrite the previous one?

-          When the processor read the previous X/Y coordinate after the TSC2006 has finish processing the new Y coordinate but not the new X coordinate is it guarantee the X and Y position the processor get come from the same conversion cycle?

-          When the processor read an X/Y coordinate at the exact same time the TSC2006 is updating its X and Y registers is the data the processor will get be valid?  Is it guarantee the X and Y position the processor get come from the same conversion cycle?  Is the content from X or Y register can be corrupted?

The following questions are regarding the test conditions for the VOH and for the VOL of the TSC2006. 

-          In the data sheet, the test conditions say IOH and IOL are 2 TTL loads but I don't know what is a TLL load. What are the IOH and the IOL current for one TTL load?  Is the magnitude of IOH and IOL are the same?

-          There is no IBIS model for the TSC2006 but there is one for the TSC2008.  Is the IBIS model for the SDO and PINTDAV outputs of the TSC2008 can be use for the TSC2006.

      Teodor

   

  • 0
    TI__Guru**** 180961 points

    Hi Teodor,

    For IOH and IOL, one TTL unit load is defined as 40 µA for a logic 1 and -1.6 mA for a logic 0.  The IBIS model would be different, as the model is dependent on the actual package.  We will check with the modeling team to see when the IBIS model for the TSC2006 will be available.

  • 0 in reply to Tom Hendrick
    Intellectual 260 points

    Few more questions Tom:

    The TSC2006 will be powered from the 3.0 volts supply rail, the conversion clock will be programmed to 2 MHz and the resolution will be programmed to 12 bits.

    -          Setting the “ Power Not Down Control ” (PND0) to ‘0’ or to ‘1’ has any consequence on the resolution of the A/D converter ?

    -          If I set the “ Power Not Down Control ” (PND0) bit to ‘1’ and the “ Converter Function Select ” (C3-C0) bits to ‘0001’ (scan X and Y) is the A/D converter biasing circuitry will always be on ? 

    -          Is it OK to set the “ Conversion Clock Control ” (CL1-CL0) bits to ‘01’ (2 MHz) when the SNSVDD power is 3.0 volts and the resolution is programmed to 12 bits ?

    -          Is it OK to set the “ Longer Sampling Mode ” (LSM) bit to ‘0’ when the SNSVDD power is 3.0 volts and the resolution is programmed to 12 bits ?

    -          Does the hardware RESET signal need to be a pulse?  I ask the question because the power on reset (POR) on our system start low (‘0’) and go high (‘1’) 800 millisecond after all supply rails are OK.  It’s not a pulse it’s a step with 800 millisecond of low time. 

    -          Regarding my previous set of questions, can you please verify if the X and Y values are write protected during read access to prevent the case where one or the other value is from a different conversion cycle.

  • 0 in reply to Teodor Neagoe
    TI__Genius 9725 points

    I put my answers next your question in green below:

    Setting the “ Power Not Down Control ” (PND0) to ‘0’ or to ‘1’ has any consequence on the resolution of the A/D converter ?  No, PND0 has nothing to do with the resolution of the A/D converter.

    -          If I set the “ Power Not Down Control ” (PND0) bit to ‘1’ and the “ Converter Function Select ” (C3-C0) bits to ‘0001’ (scan X and Y) is the A/D converter biasing circuitry will always be on ?  If PND0 bit is set to "1" , the A/D converter biasing circuitry will always be on after each conversion.

    If Is it OK to set the “ Conversion Clock Control ” (CL1-CL0) bits to ‘01’ (2 MHz) when the SNSVDD power is 3.0 volts and the resolution is programmed to 12 bits ? Yes, it is fine.

    -          Is it OK to set the “ Longer Sampling Mode ” (LSM) bit to ‘0’ when the SNSVDD power is 3.0 volts and the resolution is programmed to 12 bits ? Yes, it is fine.

    -          Does the hardware RESET signal need to be a pulse?  I ask the question because the power on reset (POR) on our system start low (‘0’) and go high (‘1’) 800 millisecond after all supply rails are OK.  It’s not a pulse it’s a step with 800 millisecond of low time. Yes, it is an acceptable power up sequence.

    -          Regarding my previous set of questions, can you please verify if the X and Y values are write protected during read access to prevent the case where one or the other value is from a different conversion cycle. To make sure you read data in the same cycle, you need to check the /DAV status of the /PINTDAV pin. You may call me (214 567 4838) between 8:30am to 5:00pm CST weekday if you have further questions or need more explanations.