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DAC8728: CLR Pin problem

Hans Wu6
Prodigy 60 points
Part Number: DAC8728


Hi,

In the datasheet, p.38 CLR' 

I take a truth table of DAC OUTPUT by CLR' and LDAC'

CLR’

LDAC’

DAC OUTPUT

LOW

LOW

X, Output are cleard to 0V

LOW

HIGH

X, Output are cleard to 0V

HIGH

LOW

Set DAC output

HIGH

HIGH

Remain cleard until LDAC is taken low

I don't know what's the meaning of " Remain cleard until LDAC is taken low ", it meaning clear to zero?

If yes, what's the different with the CLR' = low while the LDAC' = low/high?

thanks! 

  • 0
    Prodigy 60 points
    BY the way, I set LDAC' default = high for synchronous mode
  • 0 in reply to Hans Wu6
    TI__Mastermind 46290 points
    Hans,

    Yes - more or less CLR comes at a higher priority than the state of the LDAC pin or the digital register contents. If CLR is held low, the outputs will remain in the "clear" state, which in this case means that they will be tied to a 15kOhm resistor to GND. When CLR goes high the outputs will remain in that state until LDAC is taken low, at which point the outputs will return to the output value defined by the register contents.
  • 0 in reply to Kevin Duke
    Prodigy 60 points
    Hi Kevin,

    Yes, so I have another question abuot datasheet's description below
    "When CLR is taken high again while the LDAC is high, the DAC outputs remain cleared until LDAC is taken low."
    Is there a comma missing between remain and cleared ?

    Thanks!
  • 0 in reply to Hans Wu6
    TI__Guru 54323 points
    Hi Hans,

    There is not a comma in that statement. If you assert CLR high, the DACs will not return to the original value until the LDAC line is brought low again. If LDAC was held low the entire time, the DACs would resume after the CLR is set high.

    Thanks,
    Paul