AMC7834: CLAMP Configuration (0x17) R/W problem

Michael Owen

Part Number: AMC7834

Should all of the bits 0..6 in CLAMP Configuration (0x17) be readable to indicate their status? I find that Bit 6 (PAON) does change to reflect its status, but the lower Bits 0..5 do not. I can successfully write to Bits 0..5 to toggle them and clamping/unclamping has the desired effect on the DACs, but reading the bits always returns TRUE (1) whether they are clamped or not. Is this expected behavior, or perhaps I am missing something?

Thank you -

over 6 years ago

0 Paul_Frost over 6 years ago

TI__Guru 53923 points

Hi Michael,

I will confirm this in the lab after the holiday.

Thanks,
Paul

0 Paul_Frost over 6 years ago in reply to Paul_Frost

TI__Guru 53923 points

Hi Michael,

The bits will clear immediately if the SNOOZE bits of the SLEEP1 and SLEEP2 register are set to 0. If they are set high, and the device enters a sleep mode, the DACs will enter clamp. If the SNOOZE bits are enabled, they will stay in clamp until the CLAMP register is written.

If you are just writing to the clamp register to enter and leave clamp mode, then they should read back the correct value given their state.

Thanks,
Paul

0 Michael Owen over 6 years ago in reply to Paul_Frost

Prodigy 100 points

Thanks, Paul - great support!

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AMC7834: CLAMP Configuration (0x17) R/W problem