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AFE5818: TX_TRIG Timing

Part Number: AFE5818

Hello,

My customer has a question about AFE5818.

[Q]

Does the following mean the same thing?

If the answer of above is Yes, which value is correct?

<Setup time related to latching TX_TRIGD relative to the rising edge of the system clock>

* tSU_TX_TRIGD=0.6ns(typ) in D/S P.20

* t_setup=3.6ns in D/S P.55 Figure 84

<Hold time related to latching TX_TRIGD relative to the rising edge of the system clock>

* tH_TX_TRIGD=0.4ns(typ) in D/S P.20

* t_hold=1ns in D/S P.55 Figure 84

Best Regards,

Hiroshi Katsunaga

  • Hi Hiroshi-san,

    How are you?
    Thank you for helping customer using AFE5818 device.
    We will look into the detail of the TX_Trig timing
    and I will reply to you very soon.

    Thank you and best regards,
    Chen
  • Hi Hiroshi,

    How are you?
    Yes, for the customer's questions:
    TX_TRIGD is the internally delayed (please compared to TX_TRIG pin) version
    of TX_TRIG (please note: TX_TRIG is the external pin).
    According to the AFE5818 data sheet mentioned (page 20):
    There would be a Delay between TX_TRIG and TX_TRIGD
    (delay range: could be around 0.5ns to 0.4*Tclkin second)

    Therefore for the data sheet showing the limit:
    1) for the Setup time:
    TX_TRIG rising edge set to be 3.6ns before the Clock (referred to System Clock's rising edge)
    then TX_TRIGD rising edge could be 0.6ns before the Clock (referred to System Clock's rising edge)
    2) for the Hold time:
    TX_TRIGD falling edge could be 0.4ns after the Clock (referred to System Clock's rising edge)
    then TX_TRIG falling edge would set to be 1ns after the Clock (referred to System Clock's rising edge)

    Thank you very much!

    Best regards,
    Chen
  • Hi Chen-san,

    I'm fine, thank you, and you ?

    Thank you for your fast response and giving your clear comments.

    I understood your comments.

    Thank you for your cooperation !

    Best Regards,

    Hiroshi Katsunaga