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Original question:

ADC12DJ2700: Recommended method of interfacing an LVPECL source for this TMSTP input?

ADC12DJ2700: Recommended method of interfacing a LVDS source for the TMSTP inputs

Gil Hershman71
Intellectual 580 points
Part Number: ADC12DJ2700

hello,

I have a LVDS output from a Xilinx Ultrascale and would like to connect it to the TMSTP inputs, and use it as JESD204B SYNC.

I understand that when TMSTP is used as JESD204B SYNC, it requires an active low signaling, thus DC coupling is required.

Can you recommend on a way to do so?

Xilinx LVDS spec:

Thank you

Gil

  • 0
    TI__Genius 12780 points

    Hi Gil,

    One of our experts is taking a look into your inquiry, and will get back with you shortly.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    TI__Mastermind 44680 points
    Hi Gil
    Due to the low common mode voltage requirement of the TMSTP inputs we highly recommend using the /SYNCSE input for JESD204 SYNC purposes.
    You can either use an LVCMOS output from the Xilinx FPGA, or use an LVDS output pair and convert to SE using a discrete LVDS to LVCMOS converter IC to drive the /SYNCSE input.
    I hope this is helpful.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Intellectual 580 points

    Hi Jim,

    Thank you for clarifying and recommending a better use for the JESD204B SYNC.

    Currently, the Xilinx JESD204 IP uses a LVDS interface.

    We will make an effort to change it to CMOS or use an external LVDS-CMOS converter.

    I'd still appreciate a solution for my question.

    If TI designed such an interface with low CM requirements, surely it can be met.

    Thank you

    Gil

  • 0 in reply to Gil Hershman71
    TI__Mastermind 44680 points
    Hi Gil
    The TMSTP+/- inputs use similar input circuitry to that of the CLK+/- and SYSREF+/- inputs. This was done to give better performance matching between those inputs and the signal applied to TMSTP. Unfortunately this means the DC-coupled TMSTP or /SYNC signal must meet the low common mode voltage requirements, which is not compatible with LVDS. There is no way to convert from the FPGA LVDS outputs to the TMSTP+/- inputs using discrete terminations. Using a resistor divider to achieve the needed common mode will result in the differential amplitude being lower than what is needed. The only solution is to use an LVDS to LCPECL or LVPECL buffer IC along with some additional board level termination resistors and set TMSTP_LVPECL_EN = 1.
    When using an FPGA LVDS output for JESD204B /SYNC a conversion IC is needed in either case. Therefore for simplicity we recommend using the /SYNC_SE input instead of the TMSTP+/- inputs.
    Best regards,
    Jim B