ADC12020: trigger for Data conversion

Hi Nagata-san

Please refer to the ADC12020 datasheet Block Diagram, Timing Diagram and description of the CLK input signal.

The input signal is sampled tAD (time of aperture delay) after the rising edge of CLK. The CLK input should be a continuous approximately 50% duty cycle clock signal with low jitter. Other requirements of the CLK input are listed in the DC and Logic Electrical Characteristics and AC Electrical Characteristics tables.

When the /OE (active low output enable input) is asserted, the output data corresponding to that sampled input is available on the output DO0-11 output pins 6 clock cycles later.

An example application circuit is shown in Figure 40 of the datasheet.

Best regards,

Jim B