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ADS1293: Clock domains and buffers

tim etchells
Prodigy 100 points
Part Number: ADS1293

I have 2 questions on the ADS1293.

1.I am planning to run with an external clock for noise issues, are there any internal clocks that are not slaved to the CLK input that might cause noise issues?

2. Is it possible to run without the DRDYB signal without loosing data? ie how big is the buffer and is the information available in a register to poll? so is there another way of detecting there is good data and if we miss a data ready how long do we have before the data is stale.  if it helps we plan to run the SPI bus at a multiple of the CLK drive.

thanks

tim

  • 0
    TI__Guru 55062 points
    Hi Tim,

    Thanks for your post and welcome to the forum!

    If you disable the internal clock and use an external clock then there should not be any other sources of noise.

    It is possible to run data collection without monitoring DRDYB, however it becomes more difficult to adjust the timing - especially over long periods of time. There is one additional conversion worth of data in the register that can be pulled, and the data is lost if not collected before the next DRDYB is issued.

    'From the datasheet:
    "New data is available regardless of the serial interface being ready to read the data or not, and therefore, the data is lost if it is not read before the next DRDYB assertion. If DRDYB is asserted and the data is not read, DRDYB is automatically deasserted at least tDRDYB seconds before the next DRDYB assertion. The value for tDRDYB can be found in Figure 1 and Figure 2."