• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 607 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC1220: SPI communication

Michael Buck
Prodigy 40 points
Part Number: DAC1220

Hello TI,

I just have a quick question about using the DAC1220 in a design. I am using 3-wire SPI and was wondering if it is okay if I use multiple devices on the same bus in this configuration with this specific chip?

Thank you for your time,

Michael

  • 0
    TI__Mastermind 46290 points
    Michael,

    Per the datasheet this configuration is allowed, however I would call out the comments on page 8, also pasted below:

    "The serial clock is limited to one-tenth of the master clock frequency. For a 2.4576MHz master clock, the serial clock may be no faster than 254.76kHz. The designer should bear this in mind, as it may prevent the DAC1220 from being shared with other SPI devices or placed on an SPI bus, which may run much faster."
  • 0 in reply to Kevin Duke
    Prodigy 40 points
    Hello Kevin,

    I am aware of this section of the datasheet, My question is am I able to have three DAC1220s on one 3-Wire SPI Bus without
    any sort of communication issues or by doing so am i setting myself up for problems?

    Best regards,

    Michael
  • 0 in reply to Michael Buck
    TI__Mastermind 46290 points
    Michael,

    Though I have not tested this myself, I do not see any reason why it would not work.

    Page 11 indicates that when CS is high all activity on SCLK is ignored by the device, so from the DAC1220 perspective it should not be impacted when interfacing other devices.

    Though it is not explicitly stated, I believe the default state of the SDIO pin is high-z, basically in input mode, so the DAC1220 would not impair other activity on the bus either. SDIO is only driven by the DAC1220 when a register read is performed, which would imply the DAC1220 CS pin is driven low. I am basing this assumption on the last paragraph on Page 8 in the "Serial Interface" section.