[FAQ] How do I reject undesired frequency content by adjusting the clock frequency or oversampling ratio of a Delta-Sigma ADC?

Before explaining how the clock frequency of a Delta-Sigma ADC influences its digital filter frequency response it will be beneficial to get a basic understanding of the digital filters typically used in Delta-Sigma ADCs.The following application note provides a brief overview: Digital Filter Types in Delta-Sigma ADCs

It will also be beneficial to understand how the delta-sigma ADC digital filter scales with clock frequency as explained in this FAQ thread.

Adjusting the frequency location of the SINC filter notches can be utilized to reject specific interferers in the frequency spectrum.
In industrial applications it is often required to filter out interference from the 50 Hz or 60 Hz mains. The mains frequency usually varies by a few 100 mHz over time. Fortunately, the filter notch of a SINC3 filter when set at 50 Hz or 60 Hz is pretty wide to guarantee attenuation of typically ~100 dB even when the mains frequency changes by ±1 Hz.
It is possible to achieve even higher attenuation by periodically measuring the mains frequency and adjusting the ADC clock frequency to ensure the location of the digital filter notch tracks the frequency location of the interference. Means that the interference remains in the deepest part of the filter notch.

Similar concepts can be applied to Delta-Sigma ADCs that use a wide-bandwidth/flat passband digital filter. The ADS127L01 is an example of an ADC having this type of filter option.
One of the key features of those wide-bandwidth filters is that they offer very high stopband rejection at frequencies above the Nyquist frequency.
Let's assume you use ADS127L01 with the following settings: WB2 Filter, f_CLK = 16.384 MHz, OSR = 128, HR mode. The resulting output data rate is 128 kSPS and the stopband of the digital filter starts at 64 kHz.
During evaluation or operation you realize there is a strong interferer at 55 kHz. Adjusting the external analog low-pass filter to reject this interferer is not easily accomplished during operation. It also requires an active analog filter with a very high order to achieve a transition as steep as the ADS127L01 digital filter.
The solution to this problem could be one of the following:

• You could select a higher OSR setting of ADS127L01, which yields a lower output data rate but also lowers the start of the stopband region.
  The OSR settings are usually only adjustable by powers of 2. When increasing the OSR of ADS127L01 to 256, the stopband starts at 32 kHz and therefore attenuates the interferer at 55 kHz. However, limiting the passband to 25.6 kHz might not be acceptable in the application.
  
  
• The better approach might therefore be to reduce the external clock frequency to e.g. 12.8 MHz. This moves the start of the stopband to 50 kHz, rejects the interferer at 55 kHz, but also still maintains a wide passband of 40 kHz.

The following diagram illustrates the frequency response of the digital filter using the above mentioned settings.

Regards,