Hello, TI expert
On ads1282 based custom board, the sync signal seem not functional in a very low possibility (about 1%)? That means in that case drdyn does not appear on a delay described on datasheet(62.98046875/fDATA + 468/fCLK), it appears less than one sample interval after sync event.
1. the sync signal is about 1s low level and then pulled high
2. the reset signal is always at logical level 1
3. the power down signal is always at logical level 1
What might be the problem or I misunderstand something?
Best Regards
Yang
