ADS52J90: Multiple synchronization

Hi Kuramochi-san,

How are you?
Thank you for helping ADS52J90 customer.
We will look into synchronization issue as the customer mentioned.
I will reply you very soon.

Thank you very much!

Best regards,
Chen

Chen-san,

Thank you for your support.

We have additional questions.

1. Could you tell me why t5 affected to synchronization?

2. If system clock and TX_TRIG inputted into multiple chips simultaneously, they may not synchronize by different delay time as below.

    Is it correct?    

3. Is falling edge of TX_TRIG related to device synchronization?

   (We're assuming that it is not.)

4. After writing 0x3000 into 0x0a, should we write 0x0000 into 0x0a?

   (We're assuming that it is not necessary.)

Best Regards,

Kuramochi

Hi Kuramochi-san,

How are you?

Thank you for helping customer using ADS52J90 device.

First, could please confirm the following sequences and input settings and register settings 

(highlighted with blue color) with the customer.

Because they are needed and very important for synchronizing the devices purpose.

Thank you so much!

For the question #1:

Right now we don't know where is the problem coming from yet,

we suspect at Low temp test for the timing of RESET

the device may need to take longer time to reset the whole system inside the unit.

So far we just suggest the customer to try it and see if it could help the issue

and don't have any conclusion yet.

For the question #2:

As long as both the system clock and TX_TRIG input into multiple chips at the same time

by following the data sheet spec. condition (requiring: min=0.5ns ~ max=0.4*ts),

they should be able to be synchronized

However for running at Low temp, if this condition becomes different.

then Sorry, please let me contact with the design team to double check on this?

Thank you!

For the question #3:

No, the falling edge of TX_TRIG does not take any action of synchronization.

For the question #4:

After setting the Initialization register to (software setting) Address=0x0A, Data=0x3000

and then its register will self-clean to Data=0x0000

Thank you very much!

Best regards,

Chen

Chen-san,

Thank you for your support.

I wait answer for #2.

I have an additional question.

If multiple TX_TRIG pulse inputted as below, which trigger(A or B) is recognized?

Best Regards,

Kuramochi

Chen-san,

Thank you for your support.

About #2, I'm considering that TX_TRIG pulse should rise up during previous SYSCLK high term to synchronize each chip as below.
Because sum of tTX_TRIG_DEL and tSU_TX_TRIGD is shorter than 1/2 cycle of SYS CLK, so conversion timing is not affected to these delay and should accord.

>For your multiple TX_TRIG pulses:
>Only Trigger B (the latest) would be recognized.

I see.

Best Regards,
Kuramochi

Hi Kuramochi-san,

How are you?
Please take a look here is more detail explanation from our team system engineer:
Thank you!

==============
The delay between TX_TRIGD" and TX_TRIG depends on
when TRIG trig is applied, or ADC CLK freq is.

The max is 0.4TCLK, so the TX_TRIG setup time
would be 0.4TCLK+0.6ns minimal refer to
the ADC rising edge of the CLK.

Hold time min(=0.5ns) would be 0.5ns delay+0.4ns=0.9ns
refer to the ADC rising edge.

An easy to meet configuration would be

• TX_TRIG: width= 1 ADC CLK cycle

• TX_TRIG aligned with ADC CLK’s falling edge.

• After the delay, worse delay is 0.4TCLK,
so we still have 0.1CLK as the Setup time.
for CLK as high as 80MHz, 0.1CLK=1.25ns is still enogh
for 0.6ns setup time.

• The shorted delay is 0.5ns.
so the hold time is 0.5ns and still meet
the 0.4ns hold time for H_TX_TRIGD.

• I know it is theoretical calculation.
==============

Thank you and best regards,
Chen

Chen-san,

Thank you for your support.

I have any questions.

>• TX_TRIG aligned with ADC CLK’s falling edge. 

How about after from CLK's rising edge to ADC CLK’s falling edge?

>• The shorted delay is 0.5ns. 
>so the hold time is 0.5ns and still meet the 0.4ns hold time for H_TX_TRIGD.

Why do the delay(0.5ns) and the hold time concern?

I consider that each are dependent.

Best Regards,

Kuramochi

Hi Kuramochi-san,
How are you?
Thanks!
Yes, I will forward your question to our team system engineer again.

Thank you very much!

Best regards,
Chen

Chen-san,

How is this situation?

Best Regards,
Kuramochi

Hi Kuramochi-san,
How are you?
Yes, I am preparing some plots for you
but it may take 1-2 days.
Then I will send out to you very soon after that.
Sorry for the waiting.

Best regards,
Chen