[FAQ] ADC Noise: Can clocks affect your ADC’s noise performance?

Although you may expect an ADC’s sampling period to be perfectly constant, there is always some deviation from the ideal. “Clock jitter” refers to the variation in a clock waveform’s edges from one period to the next. Since all ADCs use a clock edge to control the sampling point, clock-edge variation creates deviations in the sampling instance. This deviation results in a non-constant sampling frequency that appears in the conversion result as another source of noise. Figure 9 shows the sampling-edge variation caused by clock jitter on a sinusoidal input signal.

Figure 9: Clock signal showing sampling-edge variation caused by jitter

To learn how clocks cause additional errors, as well as ways to reduce system noise due to clocking, read part 10.

While these are some of the most important questions answered in the “Resolving the Signal” series, I covered many more topics and examples to help you get the best noise performance out of your high-resolution, delta-sigma ADC signal chain. Read the series to learn more, and if you have any additional questions, feel free to post them in the comments below.