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ADC0808-N: Power Sequence for VCC and VREF?

Jason Lo
Prodigy 250 points
Part Number: ADC0808-N
Other Parts Discussed in Thread: TLV4170

I am troubleshooting an issue on a design that uses an ADC0808-N.  One observation I have made is that I get different behavior depending on whether I apply voltage to the VCC pin before VREF, or vice versa.

SETUP:

The VCC pin is receiving power from a +5 V supply and is connected directly to the power rail.

The VREF+ pin is connected to +5 V derived from a separate power supply than the VCC +5 V rail.  The derived +5 V goes through an op-amp voltage follower (TLV4170) who's output is then connected to VREF+.

The VREF- pin is connected to ground.

TEST:

When I am powering up the ADC, if I apply voltage to VCC first, and then to VREF+, the ADC works as expected.

However, if I apply voltage to VREF+ first, and then to VCC, I notice that the VREF+ plus pin has dropped from +5 V to about +4.6 V.  The output of the voltage follower has dropped to +4.6 V even though its input is still at +5.0 V.  It seems like the ADC is in some state where the VREF+ pin is loading down the op-amp.

Anyone know anything about this behavior?  Any ideas would be appreciated!

  • 0
    TI__Guru**** 174386 points
    Hi Jason,

    Please take a look at page 2 in the ADC0808 datasheet. There are restrictions listed there on the voltages applied to various pins with respect to the Vcc rail. VREF should not exceed Vcc by more than 300 mV, so when you bring up VREF first I suspect you are turning on an ESD diode inside the package and getting into a weird semi-latch-up state. Does the ADC0808 actually continue to work in that condition? I suspect it may have irregular outputs. Please drive Vcc first, keeping VREF followed by or tracking along with the Vcc and you should be fine.
  • 0 in reply to Tom Hendrick
    Prodigy 250 points

    Thanks Tom, I have a gut feeling that the scenario you described is exactly what is happening.  You are correct that the ADC still continues to operate even after entering this semi-latch-up state - digital outputs are all off since VREF is not my expected value.

    I will experiment and mark this topic closed when I have the data.

  • 0 in reply to Jason Lo
    TI__Guru**** 174386 points
    Cool! Do let us know how you make out.
  • 0 in reply to Tom Hendrick
    Prodigy 250 points

    Tom,

    Okay, we have concluded that improper sequencing of VREF and VCC on the ADC was the cause of the error I was seeing.  This topic can be marked as resolved.  Thanks for the help!

    Regards,

    Jason