ADC12D1800: Recommended power-up sequence for NON-DES mode with sampling clock of 1800Mhz.

Hello Itay

Are you operating the data interface in non-demux mode or 1:2 demux mode? Generally when I see a sudden shift in data integrity related to clock rate I suspect a problem in the data capture or data processing functions in the FPGA.

To help understand whether the problem is related to the ADC or FPGA operation you can keep the ADC settings constant. Then configure/test the FPGA capture multiple times to see if the behavior stays the same or changes. If the behavior changes then I suspect the FPGA/firmware may be having a problem at the higher data rate. If the behavior is the same every time then the ADC configuration may not be correct.

The normal startup sequence is as follows:

1. Apply power to the ADC
2. Configure all of the control pin inputs to the desired settings
3. Turn on the ADC clock
4. Configure all of the configuration register settings as needed per datasheet and application needs. The order of writes is not critical.
5. Perform an on-command calibration, initiated by CAL pin or CAL configuration register bit.
6. Enable the FPGA data capture logic
7. If ADC temperature shifts by more than 20-30 degrees then perform an on-command calibration

Performing the ADC calibration will only re-optimize the ADC performance, it will not affect the data output timing, and should have no impact on data capture by the FPGA.

In addition to the configuration sequence also please confirm that the power supply voltages are in specification at the higher clock rate. Since the ADC current consumption increases at higher clock rates there is a chance that the supply voltage has dropped out of spec.

I hope this is helpful.

Best regards,

Jim B

Hello Itay

I have copied your comments and questions here along with my responses:

We set the NDM bit to logic low '0' - DEMUX mode (i.e. We use both DI and DID for sampling the I channel).

About the sampling logic, as mentioned, the TPM mode works fine all the time, even when the data is corrupted.

Therefore I'm pretty sure that the LVDS mechanism work fine. 

Can you send me the raw data on each ADC output port for TMP mode and for normal data mode with a very low frequency input sinewave signal? Perhaps something like 10 MHz? In my experience if the TPM data is in the correct order and is aligned correctly across the output ports, then the sinewave data should be OK as well. Using a low frequency sine helps to ensure the port data is properly aligned.

 

I wanted to ask some more specific questions about the power-up sequence (following your recommended one):

Apply power to the ADC

- I cant control the timing of the power-up. The device is fed straight from the board. Can it be a problem?

This is probably OK.

Is the ADC powered up before, after or at the same time as the following items:

• ADC logic control input drivers
• ADC clock source

In general the ADC should be powered up either before or at the same time as the logic control input levels are applied.

Configure all of the control pin inputs to the desired settings

- Following the comment from (1), I cannot assure that the device "wakes up" where all its pins are at their final state.

Turn on the ADC clock

- We use external pll devices which feed the device with fSample/4 clocks.

Is the applied ADC clock signal 1800 MHz or a lower frequency? Are these other clocks at fSample/4 used for the 

 Should I keep PDI and PDQ at logic high '1' as long as the plls are not locked? can it be a problem?

These don't need to be held at logic 1. The device can be active while the clock starts up.

Configure all of the configuration register settings as needed per datasheet and application needs. The order of writes is not critical.

- About "The order of writes is not critical." : even the timing of the writing to CAL? Shouldn't the first register be written last? 

Yo are correct, the CAL bit should be written last.

The CAL process should happen after all logic control pins are set, and all other registers are configured, with stable clock and a device operating temperature near the final expected temperature.

I hope this is helpful.

Best regards,

Jim B

Hi Itay
Are you seeing this issue with the wrong register default values on multiple ADC12D1800 devices or just a single unit?
Can you verify the ADC power supply voltage is within spec?
Can you share the schematic showing all ADC connections, power supply circuitry, etc?
Is it possible to try different power supply startup ramp rates using an external power supply?
Best regards,
Jim B