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DAC8728: Wrong output is seen at power-up

Masanori Tachibana
Genius 5350 points

Part Number: DAC8728

Hi support team,

On our customer's board, wrong behavior of the DAC8728 is seen at power on.

[Symptom]
When power is turned on, all output signals of DAC8728 are fixed to +Full-Scale voltage at about once every several tens of times.
The symptom occurs when the power is turned on.
And it occurs even when the pin RSTn is not deasserted at power on.

If it becomes this state once, no external bus can access.
Also, even if the pin RSTn is asserted and deasserted, the outputs are not reset.
However, if the pin CLRn is asserted, the outputs will be 0 for that period. And they will return to +Full-Scale output when it is deassert .

[Operating condition of DAC8728]
AVDD : +15 V
AVSS : -15 V
DVDD : +5 V
IOVDD : +3.3 V
REF - A and REF - B : +4.096 V (applied from external reference voltage)
USB / BTC pulls up to IOVDD with 10 kΩ
RSTSEL pulls up to IOVDD with 10 kΩ
LDAC is connected to DGND (used fixed at low)

Are there any possible causes?
I'd like you to give me some advice.

Sincerely,
M. Tachibana

  • 0
    TI__Genius 14220 points
    Hi Masanori,

    Thank you for your query. I could not look into the issue today. I will get back to you by tomorrow.

    Regards,
    Uttam Sahu
    Applications Engineer, Precision DACs
  • 0 in reply to Uttam Sahu
    TI__Genius 14220 points
    Hi Masanori,

    Apologies for the delay. There is a power-supply sequencing requirement for this device. It is described on page 41 of the datasheet. Please check whether you are following that or not. I am suspecting a problem with the supply sequencing.

    Regards,
    Uttam
  • 0 in reply to Uttam Sahu
    Prodigy 10 points
    Hello Uttam,

    I am also looking for information on the power supply sequencing. I see that IOVDD/DVDD should come first, then AVDD, and lastly REF-x pins. However, is there a minimum timing needed between applying power to each set of pins?

    Thank you,
    Kyle
  • 0 in reply to Kyle Kellenberger
    TI__Genius 14220 points
    Hi Kyle,

    There is no specific timing requirement. But you should make sure the sequencing is maintained even during the ramp-up. Usually is happens that the power supplies are sequanced as per datasheet and due to unequal ramp-up times, they may violate the sequencing condition at power-up.

    Is it possible for you to share a scope shot of the power supply ramp for me to look at? It will be good if you can upload a snapshot of the DAC portion of the schematics as well.

    Regards,
    Uttam
  • 0 in reply to Uttam Sahu
    Genius 5350 points
    Hi Uttam-san,
    Apologies for the late reply.

    After changing the power-up sequence, the symptom seems to have improved.
    In case that the voltage of AVDD (+15 V) exceeds 2.5 V before the DVDD (+5 V) and IOVDD (+3.3 V) are stabilized, the symptom seems to occur more frequently.

    Sincerely,
    M. Tachibana