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ADS131E04: Propagation Delay between CLK to DRDY?

Martin Seeger
Expert 5411 points
Part Number: ADS131E04

Dear Team,

our customer would like to use the ADS131E04 and has a question about the propagation Delay between CLK to DRDY.

Do you have any value for this?

Thanks and best regards
Martin

  • 0
    TI__Guru* 97775 points
    Martin,


    I'm not sure I understand the question. If you're asking about the delay from the conversion start to the settled data, this device uses a sinc3 filter, and takes 3 conversion cycles to settle the data.

    Settling time is discussed in the datasheet on page 28 of the datasheet. Once the conversion is started, there is a moving average of 3 samples taken (as a sinc3 filter), for which the first two samples are suppressed and the third indicates that the data is ready. There is also some added acquisition time as the ADC calculates the average and gives an output data. Subsequent data comes out at 1/DR period.

    If you want a basic propagation delay, this might be the delay from the 3*(1/DR) subtracted from settling time from Table 5. This would be different for each data rate.

    Hopefully this answers the question. If I've misunderstood the question or you want clarification, post back and we can continue the thread.


    Joseph Wu
  • 0 in reply to Joseph Wu
    TI__Expert 5411 points

    Hello Joseph,

    thanks a lot for the swift reply.

    Apologies for the misunderstanding. My question was rather related to the propagation delay time between CLK and DRDY. Similar to the ones spec'ed in table 7.7 on page 12. 

    Since DRDY is directly connected to the controller (shown in the block diagram), we are not sure if we can apply the CLK to DOUT spec to this case. DOUT is part of the SPI interface, so we expect CLK to DRDY to be shorter?

    Hope it makes sense.

    Thanks and best regards
    Martin

  • 0 in reply to Martin Seeger
    TI__Guru* 97775 points
    Martin,


    I'm still not entirely sure what you are asking for. I assume that you are referring to SCLK (from the SPI communication) instead of CLK (which is the master clock typically run at 16.384 MHz). In 7.7 there is a propagation delay time given as tp(SCDOD). This time indicates the time from the rising EDGE of SCLK to setup the output data on DOUT. A change in SCLK directly changes DOUT.

    However, SCLK doesn't directly drive /DRDY. You can set up a conversion through a command, but the time that it takes to complete a conversion is based on the data rate. For that you wouldn't have a propagation delay spec. Even if you are referring to the master clock, the DRDY comes after a great number of master clock periods after a conversion is started. Generally there isn't a propagation delay specification from either clock to the /DRDY indication. Perhaps you could ask the customer to clarify the need for the specification.


    Joseph Wu
  • 0 in reply to Joseph Wu
    TI__Expert 5411 points
    Hello Joseph, thanks for the answer. I reached out to you offline. Best Regards, Martin